E0C624A Datasheet PDF
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WOPidpreeordVauoticlottansge
PF647-05
E0C624A
4-bit Single Chip Microcomputer
q Core CPU Architecture
q Dot Matrix LCD Driver
q Programmable SVD Circuit/Sound Generator
s DESCRIPTION
The E0C624A is an advanced single-chip CMOS 4-bit microcomputer consisting of the E0C6200 4-bit core
CPU. The chip contains the ROM, RAM, dot matrix LCD driver, programmable SVD circuit, time base counter
and clock synchronous serial port.
Interfacing with the external memory, the E0C624A can be applied to any system requiring large memory such
as schedule reminder, and dot matrix display function.
s FEATURES
q CMOS LSI 4-bit parallel processing
q Clock ..................................................... 32.768kHz/2MHz (Max.) (selectable by software)
q Instruction set ........................................ 108 instructions
q Instruction cycle time ............................ 153µsec, 214µsec or 366µsec at 32kHz
(depending on instruction)
5µsec, 7µsec or 12µsec at 1MHz
(depending on instruction)
q ROM capacity ....................................... 6,144 × 12 bits
q RAM capacity ........................................ 640 × 4 bits
q External memory capacity .................... Read/Write 512K bits (Max.)
Read only 1M bits (Max.)
q Input port ............................................... 8 bits (pull-up resistors are available by mask option)
q Output port ............................................ 20 bits (clock output or buzzer output is available by mask option)
q I/O port .................................................. 16 bits (pull-up resistors are available by mask option)
q Serial I/O port ........................................ 1 port (clock sync.)
q Dot matrix LCD driver ........................... 40 segments × 8 commons/40 segments × 16 commons
(1/8 or 1/16 duty is selectable by mask option)
q Built-in SVD circuit ................................ 2.3V/2.6V/3.3V/4.5V programmable
q Built-in stopwatch timer
q Built-in watchdog timer
q Built-in time base counter ..................... 3 lines
q Interrupts ............................................... External : Input interrupt
2 lines
Internal : Timer interrupt
3 lines
Serial I/O interrupt 1 line
q Built-in sound generator ........................ With digital envelope (8 sounds programmable)
q Supply voltage ...................................... 2.2V to 5.5V
q Current consumption ............................ HALT mode (32kHz)
: 2.5µA (Typ.)
OPERATING mode (1MHz) : 400µA (Typ.)
q Package ................................................ QFP5-128pin (plastic)
Die form
SEIKO EPSON CORPORATION
1 http://www.Datasheet4U.com


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E0C624A
s BLOCK DIAGRAM
ROM
6,144 words x 12 bits
System Reset
Control
RESET
Core CPU E0C6200
OSC1
OSC2
OSC3
OSC4
COM0~15
SEG0~39
V DD
V L1~5
CA~CF
V REF
V S1
V SS
R00~03, R10~13, R20~23,
R30~33, R40~43
OSC
LCD Driver
RAM
640 words x 4 bits
Power
Controller
SVD
Sound
Generator
Output Port
Interrupt
Generator
Timer
Stop Watch
Programmable
Timer
Input Port
Serial Interface
I/O Port
K00~03, K10~13
TEST
SIN
SOUT
SCLK
P00~03, P10~13,
P20~23, P30~33
s PIN CONFIGURATION
QFP5-128pin
102
103
E0C624A
INDEX
128
1
2
65
64
39
38
No. Pin name No. Pin name No. Pin name No. Pin name
1 VL3
33 SEG33 65 SEG2
97 R42
2 VL4
34 N.C.
66 SEG1
98 N.C.
3 VL5
35 SEG32 67 SEG0
99 R41
4 CF
36 SEG31 68 SCLK 100 R40
5 N.C.
37 SEG30 69 N.C.
101 R33
6 CE
38 SEG29 70 SOUT 102 R32
7 CD
39 SEG28 71 SIN
103 R31
8 CC
40 SEG27 72 K13
104 R30
9 CB
41 SEG26 73 K12
105 R23
10 CA
42 SEG25 74 K11
106 R22
11 COM0 43 SEG24 75 K10
107 R21
12 COM1 44 SEG23 76 K03
108 R20
13 COM2 45 SEG22 77 K02
109 R13
14 COM3 46 SEG21 78 K01
110 R12
15 COM4 47 SEG20 79 K00
111 R11
16 COM5 48 SEG19 80 P33
112 R10
17 COM6 49 SEG18 81 P32
113 R03
18 COM7 50 SEG17 82 P31
114 R02
19 COM8 51 SEG16 83 P30
115 R01
20 COM9 52 SEG15 84 P23
116 R00
21 COM10 53 SEG14 85 P22
117 VSS
22 COM11 54 SEG13 86 P21
118 RESET
23 COM12 55 SEG12 87 P20
119 TEST
24 COM13 56 SEG11 88 P13
120 OSC4
25 COM14 57 SEG10 89 P12
121 OSC3
26 COM15 58 SEG9
90 P11
122 VS1
27 SEG39 59 SEG8
91 P10
123 OSC2
28 SEG38 60 SEG7
92 P03
124 OSC1
29 SEG37 61 SEG6
93 P02
125 VDD
30 SEG36 62 SEG5
94 P01
126 VREF
31 SEG35 63 SEG4
95 P00
127 VL1
32 SEG34 64 SEG3
96 R43
128 VL2
N.C. = No Connection


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E0C624A
s PIN DESCRIPTION
Pin name
VDD
VSS
VS1
VL1–VL5
VREF
CA–CF
OSC1
OSC2
OSC3
OSC4
K00–K03, K10–K13
P00–P03, P10–P13
P20–P23
P30–P33
R00–R03, R10–R13
R20–R23, R30
R31
R32
R33
R40
R41
R42
R43
SIN
SOUT
SCLK
SEG0–39
COM0–15
RESET
TEST
Pin No.
125
117
122
127, 128, 1–3
126
10–6, 4
124
123
121
120
79–72
95–88
87–84
83–80
116–104
103
102
101
100
99
97
96
71
70
68
67–35, 33–27
11–26
118
119
In/Out
I
I
O
I
O
I
O
I
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
O
I/O
O
O
I
I
Function
Power source (+) terminal
Power source (-) terminal
Oscillation and internal logic system regulated voltage
LCD system power (1/4 or 1/5 bias may be selected by mask option)
LCD system power test terminal
Booster capacitor connecting terminal
Crystal oscillation input terminal
Crystal oscillation output terminal
Ceramic or CR oscillation input terminal (selected by mask option)
Ceramic or CR oscillation output terminal (selected by mask option)
Input terminal (Use of pull up resistor is selected by mask option)
I/O terminal (Setting for data bus may be selected by mask option)
I/O terminal (CS output may be selected by mask option)
I/O terminal
Output terminal (Setting for address bus may be selected by mask option)
Output terminal (DC, address or WR output may be selected by mask option)
Output terminal (DC or RD output may be selected by mask option)
Output terminal (DC or SRDY output may be selected by mask option)
Output terminal (DC, CL or FOUT output may be selected by mask option)
Output terminal (DC or FR output may be selected by mask option)
Output terminal (DC, BZ or FOUT output may be selected by mask option)
Output terminal (DC or BZ output may be selected by mask option)
Serial interface input terminal
Serial interface output terminal
Serial interface clock input/output terminal
LCD segment output terminal
LCD common output terminal
Initial reset input terminal
Test input terminal
s BASIC EXTERNAL CONNECTION DIAGRAM
LCD PANEL 120 x 16
SEG0~SEG79
SED1521FAA
DB0~DB7
Vss VDD V2 V3 V5 CL FR RES RD WR A0 CS
SEG0~SEG39
COM0~COM15
P00~P03
P10~P13
P20
P21
E0C624A
R00~R03
R10~R13
R20~R23
R30
R31
R32
K00~K03
K10~K13
P22~P23
P30~P33
SIN
SOUT
SCLK
R33
R40
R41
R42
R43
VREF
Vss
RESET
TEST
VDD
CF CE CD CC CB CA V L5 V L4 V L3 V L2 V L1 V S1 OSC4 OSC3 OSC2 OSC1
C3 C2
C1
Rfc Rfx
KEY
MATRIX
8x6
SERIAL
DEVICE
N.C.
+
Buzzer
Power
5V
Vss CS2
VDD
OE
A0~A12 WE
D0~D7 CS1
SRM2064
C7 C6
C5 C4 C8
Ceramic
Cdc Cgc
X'tal
Cgx
Rcr
Note: • Since SRM2064 is applied in the external SRAM in this example, the power
supply voltage of 5 V is used.
• The above table is simply an example, and is not guaranteed to work.
X'tal Crystal oscillator 32.768kHz
CI(Max.)=35k
Rfx Feedback resistor 10M
Cgx Trimmer capacitor 5~25pF
Ceramic Ceramic oscillator 500kHz~2MHz
Rfc Feedback resistor 1M
Cgc Gate capacitance 100pF
Cdc Drein capacitance 100pF
Rcr Resistance for
20k~100k
CR oscillation
C1~C3 Voltage booster 0.1µF 1
capacitor (1)~(3)
C4 Capacitor between 0.1µF 1
VDD and VL1
C5 Capacitor between 0.1µF 1
VDD and VL2
C6 Capacitor between 0.1µF 1
VDD and VL4
C7 Capacitor between 0.1µF 1
VDD and VL5
C8 Capacitor between 0.1µF
VDD and VS1
1 When the load on the liquid
crystal system is large, increase
the capacitance of the voltage
booster capacitors (C1–C3) and
the capacitors between VDD and
liquid crystal system power
(C4–C7).
3


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E0C624A
s ELECTRICAL CHARACTERISTICS
q Absolute Maximum Ratings
Rating
Symbol
Supply voltage
VSS
Input voltage (1)
VI
Input voltage (2)
VIOSC
Operating temperature
Topr
Storage temperature
Tstg
Soldering temperature / Time
Tsol
Permissible dissipation *1
PD
1: In case of plastic package (QFP5-128pin).
q Recommended Operating Conditions
Condition
Supply voltage
Symbol
VSS VDD=0V
Oscillation frequency (1)
Oscillation frequency (2)
Oscillation frequency (3)
Voltage booster capacitor (1)
Voltage booster capacitor (2)
Voltage booster capacitor (3)
Capacitor between VDD and VL1
Capacitor between VDD and VL2
Capacitor between VDD and VL4
Capacitor between VDD and VL5
Capacitor between VDD and VS1
fOSC1
fOSC3
fOSC3
C1
C2
C3
C4
C5
C6
C7
C8
VSC="1"
VSC="2"
Value
-7.0 to 0.5
VSS - 0.3 to 0.5
VS1 - 0.3 to 0.5
-20 to 70
-65 to 150
260°C, 10sec (lead section)
250
(VDD=0V)
Unit
V
V
V
°C
°C
mW
Remark
VSC="0"
VSC="1"
VSC="2"
(Ta=-20 to 70°C)
Min.
Typ.
Max.
Unit
-3.8 -3.0 -1.8 V
-5.5 -3.0 -2.2 V
-5.5 -3.0 -3.5 V
20 32.768 50 kHz
50 1,000 1,200 kHz
50 2,000 2,300 kHz
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
q DC Characteristics
(Unless otherwise specified: VDD=0V,VSS=-3.0V,VL1=-1.0V,VL2=-2.0V,VL4=-3.0V,VL5=-4.0V,fOSC1=32.768kHz,fOSC3=1MHz,Ta=25°C,C1–C8=0.047µF)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
High level input voltage
VHIN VSS=-2.2 to -5.5V
K00–03•10–13, P00–03•10–13 0.2•VSS
0V
Low level input voltage
VLIN Ta=25°C
P20–P23•30–33, SIN, SCLK
VSS
0.8•VSS
V
High level input voltage
VHIN VSS=-2.2 to -5.5V
RESET
-0.2 0 V
Low level input voltage
VLIN Ta=25°C
VSS
VSS+0.2
V
High level input current
IIH VSS=-3.0V
K00–03•10–13, P00–03•10–13
0
0.5 µA
VIH=0V
P20–P23•30–33, SIN, SCLK
RESET
Low level input current (1) IIL1 VSS=-3.0V
K00–03•10–13, P00–03•10–13 -45
-15 µA
VIL1=VSS
P20–P23•30–33, SIN, SCLK
With pull-up resistor RESET
Low level input current (2) IIL2 VSS=-3.0V
K00–03•10–13, P00–03•10–13 -0.5
0 µA
VIL2=VSS
P20–P23•30–33, SIN, SCLK
No pull-up resistor RESET
High level output current (1) IOH1 VSS=-2.2V
P00–03•10–13•20–23•30–33
-1.0 mA
VOH1=-0.5V
R00–03•10–13•20–23•30–33
R40•41, SOUT, SCLK
Low level output current (1) IOL1 VSS=-2.2V
P00–03•10–13•20–23•30–33
4.0
mA
VOL1=VSS+0.5V
R00–03•10–13•20–23•30–33
R40•41, SOUT, SCLK
High level output current (2) IOH2 VSS=-2.2V
R42•43
-2.0 mA
VOH2=-0.5V
Low level output current (2) IOL2 VSS=-2.2V
R42•43
8.0
mA
VOL1=VSS+0.5V
Common output current
IOH3 VOH3=-0.05V
COM0–15
-30 µA
IOL3 VOL3=VL5+0.05V
30 µA
Segment output current
IOH4 VOH4=-0.05V
SEG0–39
-10 µA
IOL4 VOL4=VL5+0.05V
10 µA
4


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E0C624A
q Analog Circuit Characteristics and Current Consumption
(Unless otherwise specified: VDD=0V,VSS=-3.0V,VL1=-1.0V,VL2=-2.0V,VL4=-3.0V,VL5=-4.0V,fOSC1=32.768kHz,fOSC3=1MHz,Ta=25°C,C1–C8=0.047µF)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
Liquid crystal drive voltage VL1 Connect 1Mload resistor between VDD and VL1
1/2•VL2
1/2•VL2
V
(Normal mode)
(No panel load)
-0.1 ×0.95
VL2 Connect 1Mload resistor
LC="0"
-1.80
between VDD and VL2
LC="1"
-1.85
(No panel load)
LC="2"
-1.90
LC="3"
-1.95
LC="4"
-2.01
LC="5"
-2.06
LC="6"
-2.11
LC="7"
Typ.×1.12 -2.17 Typ.×0.88 V
LC="8"
-2.22
LC="9"
-2.27
LC="10"
-2.32
LC="11"
-2.38
LC="12"
-2.43
LC="13"
-2.48
LC="14"
-2.53
LC="15"
-2.59
VL4 Connect 1Mload resistor between VDD and VL4
3/2•VL2
3/2•VL2
V
(No panel load)
×0.95
VL5 Connect 1Mload resistor between VDD and VL5
2•VL2
2•VL2
V
(No panel load)
×0.95
Liquid crystal drive voltage VL1 Connect 1Mload resistor
LC="0"
-0.92
(Heavy load
between VDD and VL1
LC="1"
-0.95
protection mode)
(No panel load)
LC="2"
-0.97
LC="3"
-1.00
LC="4"
-1.03
LC="5"
-1.05
LC="6"
-1.08
LC="7"
Typ.×1.12 -1.11 Typ.×0.88 V
LC="8"
-1.13
LC="9"
-1.16
LC="10"
-1.18
LC="11"
-1.21
LC="12"
-1.24
LC="13"
-1.26
LC="14"
-1.29
LC="15"
-1.32
VL2 Connect 1Mload resistor between VDD and VL2
2•VL1
2•VL1
V
(No panel load)
×0.90
VL4 Connect 1Mload resistor between VDD and VL4
3•VL1
3•VL1
V
(No panel load)
×0.90
VL5 Connect 1Mload resistor between VDD and VL5
4•VL1
4•VL1
V
(No panel load)
×0.90
SVD voltage
VSVD0 SVC="0"
-2.35
-2.20
-2.05
V
VSVD1 SVC="1"
-2.70
-2.50
-2.30
V
VSVD2 SVC="2"
-3.30
-3.10
-2.90
V
SVD circuit response time
VSVD3 SVC="3"
tSVD
-4.50
-4.20
-3.90
100
V
µS
Current consumption
Ihlt During HALT
No panel load *1
2.5 5.0 µA
IEX1 During operation at 32kHz
6.5 9.0 µA
IEX2 During operation at 1MHz
No panel load *2
400 600 µA
IEX3 During operation at 2MHz
No panel load *3
1,000 1,500
µA
1: SVD circuit: OFF status, VSC = "0", OSC1: oscillating with crystal, OSCC= "0"
2: SVD circuit: OFF status, VSC = "1", OSC1: oscillating with crystal
3: SVD circuit: OFF status, VSC = "2", OSC1: oscillating with crystal, VSS = -5.0V
5


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E0C624A
q Oscillation Characteristics
The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the follow-
ing characteristics as reference values.
OSC1 crystal oscillation circuit
(Unless otherwise specified: VDD=0V, VSS=-3.0V, Crystal: C-002R (CI=35k), CGX=25pF, CDX=built-in, RfX=10M, VSC="0", Ta=25°C)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
Oscillation start time
tsta VSS=-2.2 to -5.5V
5 Sec
Built-in capacitance (drain)
CD Package as assembled
22 pF
Bare chip
21 pF
Frequency/voltage deviation
f/V VSS=-2.2 to -5.5V
5 ppm
Frequency/IC deviation
f/IC
-10 10 ppm
Frequency adjustment range
f/CG CG=5 to 25pF
35 45
ppm
Harmonic oscillation start voltage Vhho CG=5pF
-5.5 V
Permitted leak resistance
Rleak Between OSC1 and VDD, VS1
200
M
OSC3 CR oscillation circuit (1)
Characteristic
Oscillation start time
Frequency/voltage deviation
Oscillation frequency
Symbol
tsta VSS=-2.2 to -5.5V
f/V VSS=-2.2 to -5.5V
fCR ROSC=40k
(Unless otherwise specified: VDD=0V, VSS=-3.0V, VSC="1", Ta=25°C)
Condition
Min.
Typ.
Max.
Unit
3 mS
-5 5 %
860×70% 860 860×130% kHz
OSC3 CR oscillation circuit (2)
Characteristic
Oscillation start time
Frequency/voltage deviation
Oscillation frequency
Symbol
tsta VSS=-3.5 to -5.5V
f/V VSS=-3.5 to -5.5V
fCR ROSC=20k
(Unless otherwise specified: VDD=0V, VSS=-5.0V, VSC="2", Ta=25°C)
Condition
Min.
Typ.
Max.
Unit
3 mS
-5 5 %
1.7×70% 1.7 1.7×130% MHz
OSC3 ceramic oscillation circuit (1)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, VSC="1", Ceramic: CSB 1000J (Murata Mfg. Co.), CGC=CDC=100pF, RfC=1M, Ta=25°C)
Characteristic
Oscillation start time
Symbol
Condition
tsta VSS=-2.2 to -5.5V
Min.
Typ.
Max.
Unit
3 mS
Frequency/voltage deviation
f/V VSS=-2.2 to -5.5V
-3 3 %
OSC3 ceramic oscillation circuit (2)
(Unless otherwise specified: VDD=0V, VSS=-5.0V, VSC="2", Ceramic: CSA 2.00MG (Murata Mfg. Co.), CGC=CDC=100pF, RfC=1M, Ta=25°C)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
Oscillation start time
tsta VSS=-3.5 to -5.5V
3 mS
Frequency/voltage deviation
f/V VSS=-3.5 to -5.5V
-3 3 %
6


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s PACKAGE DIMENSIONS
Plastic QFP5-128pin
102
103
23.6±0.4
20±0.1
E0C624A
65
64
INDEX
128 39
1 38
0.5 0.2±0.05
0.15±0.05
0°
10°
0.8±0.2
1.8
Unit: mm
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko
Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kindarising out of
any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that
this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to an y intellectual
property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this
material will be free from any patent or copyright infringement of a third party. This material or portions thereof may containtechnology or the
subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and mayrequire an
export license from the Ministry of International Trade and Industry or other approval from another government agency.
© Seiko Epson Corporation 1999 All right reserved.
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
IC Marketing & Engineering Group
ED International Marketing Department I (Europe & U.S.A.)
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone : 042-587-5812 FAX : 042-587-5564
ED International Marketing Department II (Asia)
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone : 042-587-5814 FAX : 042-587-5110



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