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ILLUMINANT 北極光企業有限公司
PRODUCT SPECIFICATION FOR LCM
CUSTOMER:
MODEL NO:
ACCEPTED BY:
I2501-6IGN9624B
APPROVED BY:
CHECKED BY: ORGANIZED BY:
2009.01.25
lLong
2009.01.25
Vicky
2009.01.25
Vicky
Approval for Specifications Only
Approval for Specifications and Sample
Note: 1. Version of Specifications : 1
2. Others: Rohs Compliment
TAIWAN
1F, #15, LANE 75, MIN CHUAN E. RD., SEC 3, TAIPEI, TAIWAN.
Tel +886-2-25175115 Fax +886-2-25175099
CHINA
5F DONGWU COMMERICAL BLDG., LANSHAN RD., NORTH DISTRICT, HI-TECH INDUSTRIAL PARK, SHENZHEN, PRC.
TEL + 86-755-86154466 FAX +86-755-86154366
KOREA
RM 1201, IT MIRAE TOWER, 60-21, GASAN-DONG, GEUMCHEON-GU, SEOUL, 153-801, KOREA
TEL + 82-2-2027-5391~2 FAX +82-2-2027-5393
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ILLUMINANT
Version
Date
1 09/01/25
Contents
Initial Release
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ILLUMINANT
CONTENTS
1. Mechanical Specification
2. Maximum Ratings
3. Electrical Characteristics
4. Optical Characteristics
5. Interface
6. Timing Characteristics
7. Power On/Off Sequence
8. Block Diagram
9. Backlight
10. Reliability
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ILLUMINANT
1. Mechanical Specification
Item
Display Size
Module Dimension
Active Area
Number of Dots
Surface Treatment
Display Mode
Viewing Direction
Approx. Weight
Various Color Display
Brightness
Backlight Type
Backlight Color
Standard Value
2.5
43.3(W)*60.6(H)*2.70(D)
37.44(W)*49.92(H)
960(RGB)*240 Delta Type
Clear
Transmissive Type, Positive Mode
6H
TBD
16.7M Color
250
2-LED Serial
White
Unit
inch
mm
mm
Dot
-
-
-
g
-
cd/m2
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ILLUMINANT
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ILLUMINANT
2. Maximum Ratings
If the operating condition exceeds the following absolute maximum ratings, the TFT LCD
module may be damaged permanently.
PGND=VSS=0V, Ta=25
Item
Symbol
Values
Unit Condition
Min. Max.
Power Voltage
VDD
PVDD
-0.5
-0.5
3.6
3.6
V
V
Input Signal Voltage
VCOM -2.9
5.2
V
Digital Input Voltage
VIN -0.3 VDD+0.3 V
Storage Temperature
TST -25 80
Operating Temperature
TOP
Maximum Clock Frequency
Humidity
Fmax
-
Note1 : TA≤40without dewing
0
--
-
60
30 MHZ
90 %RH Note1
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ILLUMINANT
3. Electrical Characteristics
a. Typical Operating Conditions
Item
Symbol
Supply Voltage for Source Driver VDD
Min.
3.0
Values
Typ. Max.
3.3 3.6
Uni
t
Remark
V
Supply Voltage for
Gate Driver
PVDD 3.0 3.3
H Level VGH 14 16
L Level VGL -7.5 -6
3.6
19.5
-4
V Note3-1
V Note3-1
Digital Input Voltage
H Level
L Level
VIH VDD-0.4 -
VDD
V
VIL 0 - VDD+0.4 V
H Level VOH 0.7VDD
Digital Output Voltage
L Level VOL
0
-
-
VDD
0.3VDD
V
V
VCOM
VCOMAC
VCOMDC
-
+4.5
+4.8
AC Component
Vp-p
of VCOM
- 0.24
-
V
Note 3-1 : VGH and VGL supplied by internal setup circuit.
b. Current Consumption
Parameter
Symbol Condition
Current for FOG
IDD VDD=+3.3V
Current for LCM
PIDD PVDD1=+3.3V
Typ.
6.2
35.0
Max.
12.4
70.0
Unit
mA
mA
Remark
Note1
Note2
Note 1: FOG means LCM without B/L unit
Note 2: The test conditions is by reference application note as below
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ILLUMINANT
4. Optical Characteristics
The following items are measured under stable conditions. The optical characteristics should
be measured in a dark room or equivalent state with the methods shown in Note1,2,3.
Item
Response Time
Contrast Ratio
Viewing
Angle
Hor.
Ver.
White Chromaticity
Shift
Brightness
Symbol Condition Min Typ Max Unit Remark
TR
TF
=0
-
-
20
10
30
15
ms
ms
Note 4,6
At optimized
CR viewing 200 300
angle
-
- Note 5,6
Top
Bottom
Left
Right
X
Y
CR10
=0
=0
40
20
45
45
(0.26)
(0.28)
200
45
55
65
65
(0.31)
(0.33)
250
-
-
-
-
(0.36)
(0.38)
-
Degree
-
Cd/m2
Note 6,7
Note 1 : Ambient temperature =25
Note 2 : To be measured in the dark room.
Note 3 : To be measured on the center area of panel with a field angle of 1
by Topcon luminance meter BM-7, after 10minutes operation.
Note 4 : Definition of Response time
The output signals of photo detector are measured when the input signals
are changed from “ black” to “white” (falling time) and from “white” to
“black” (rising time), respectively.
The response time is defined as the time interval between the 10% and 90%
of amplitudes. Refer to figure as below.
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ILLUMINANT
Note 5 : Definition of Contrast Ratio
Contrast Ratio is calculated with the following formula.
Contrast Ratio (CR) =
Brightness measured when LCD is at “white state”
Brightness measured when LCD is at “black state”
Note 6 : White Vi=Vi50 +1.5V
Black Vi=Vi50 ± 2.0V
“±”means that the analog input signal swings in phase with COM signal.
“+” means that the analog input signal swings out of phase with COM signal.
Vi50 : The analog input voltage when transmission is 50%.
The 100% transmission is defined as the transmission of LCD panel when all the
input terminals of module are electrically opened.
Note 7 : Definition of Viewing Angle
Refer to the figure as below.
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ILLUMINANT
5. Interface
Pin Symbol I/O
Function
1 VCOM
I Common Electrode Driving Voltage
2 CS
I Serial Command Enable
3 SDA I Serial Command Data Input
4 SCL
I Serial Command Clock Input
5 HSYNC I Horizontal Sync Input
6 VSYNC I Vertical Sync Input
7 DCLK
8 D7
9 D6
10 D5
11 D4
12 D3
13 D2
14 D1
15 D0
16 DGND
17 VDD
18 VDDIO
I Data Clock Input
I Data Input : MSB
I Data Input
I Data Input
I Data Input
I Data Input
I Data Input
I Data Input
I Data Input
P Ground Terminal in the Logic Circuit
P System Power
P Digital Voltage Input
19 DVDD C Charge Pump Power GND
20 V1
C Charge Pump Power GND
21 V2
C Charge Pump Power GND
22 V3
C Charge Pump Power GND
Remark
Note5-1
Note5-6
Note5-7
Note5-8
Note5-3
Note5-2
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ILLUMINANT
23 V4
C Charge Pump Power GND
24 VDD2
25 V5
C Charge Pump Power GND
C Charge Pump Power GND
Note5-2
26 V6
27 VDD3
C Charge Pump Power GND
C Charge Pump Power GND
28 VDD5 C Charge Pump Power GND
29 V7
C Charge Pump Power GND
Note5-2
30 V8
C Charge Pump Power GND
31 VGH
C Serial Communication Clock Input
32 VGL
C Horizontal Sync Input
33 AGND P Ground Terminal in the Analog Circuit
34 FRP
O Frame Polarity Output for VCOM
35 COMDC O VCOM DC Voltage Output Pin
36 VCAC
C Power Setting
Note5-2
37 DRV
O VLED Boost Transistor for VCOM AC Note5-4
38 VLED
P LED Power Anode
39 FB
P LED Power Cathode
Note5-5
40 VCOM
I Common Electrode Driving Voltage
Note5-1
I : Input O: Output P : Power I/O : Serial Communication Data Input/Output C : Capacitor
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ILLUMINANT
Note 5-1:VCOM=+4.8 Vp-p.(Typ.)
Note 5-2: The external capacitor is required on those pins as following.
Symbol
VGH
VGL
VCAC
DVDD
VDD/AVDD
C1P
C1M
C2P
C2M
C3P
C3M
C4P
C4M
VINT1
VINT2
VINT3
FRP/VCOMDC
Capacitor No.
C11
C12
C10
C6
C5
C1
C2
C3
C4
C7
C8
C9
C13
Part Standard
Capacitance
Voltage
≥4.7uF
25V over
≥4.7uF
16V over
≥4.7uF
10V over
≥4.7uF
6.3V over
≥4.7uF
6.3V over
≥2.2uF
10V over
≥2.2uF
10V over
≥2.2uF
16V over
≥2.2uF
16V over
≥4.7uF
≥4.7uF
≥4.7uF
≥4.7uF
10V over
16V over
25V over
10V over
Notes
Note 5-3: VDD, VDDIO=+3.3V (Typ.)
Note 5-4: Outputs the control signal of switching regulator for LED.
Duty cycle varies according to FB input voltage
Note 5-5: Feedback signal of switching signal for LED.
It controls DRV output duty cycle with 0.6V input level sense.
Note 5-6: Horizontal sync signal, it is a “Low “active signal.
Note 5-7: Vertical sync signal, it is a “Low “active signal.
Note 5-8: Dot clock signal for RGB interface, timing for data loading defined at rising edge.
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ILLUMINANT
6. Timing Characteristics
6.1. Input Timing AC Characteristics
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ILLUMINANT
Parameter
Time that the HSD
CLKIN
HSD period time
VSD setup time
VSD hold time
HSD setup time
HSD hold time
to
Symbol
Thc
Th
Tvst
Tvhd
Thst
Thhd
Data setup time
Tdsu
Data hold time
Tdhd
Time that VSD to 1st Gate
output
Tstv
Time that CCIR_V to 1st
Gate output
Tstv
Time that CCIR_V to 1st
Gate output
Tstv
Source output setting time
(*1)
Gate output setting time
(*1)
Tst
Tstg
VCOM setting time (*1)
Time that HSD width
Tst,vcom
Twh
Min.
-
60
12
12
12
12
12
12
0
0
3
-
-
-
1
Typ.
-
Max.
1
63.56
-
-
-
-
67
-
-
-
-
--
--
21 31
22 31
24 34
-8
0.5 1
-9
--
Unit
Conditions
CLKIN
us
ns
ns
ns
ns
ns
ns
H
H
H
us
us
us
CLKIN
DR0~DR7,
DG0~DG7,
DB0~DB7 to CLKIN
DR0~DR7,
DG0~DG7,
DB0~DB7 to CLKIN
@ 8-bit RGB, 8-bit
Dummy RGB
NTSC, and Parallel
RGB, Delay
by VBLK setting.
@CCIR656 NTSC,
Delay by
VBLK setting.
@8-bit Dummy RGB
& CCIR656
PAL, Delay by VBLK
setting.
R= TBD Kohm ,
C= TBD pF
10% 90%
R= TBD Kohm ,
C= TBD pF
10% 90%
R= TBD Kohm ,
C= TBD nF
10% 90%
Ps. (*1) Test Condition:
When the tested signal is changed from Vo, min to Vo, max, the time that is from the start of change
to the time that the swing voltage at point B is less than +/- 20 mV is called the setting time of the
tested signal.
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ILLUMINANT
6.2. Input Timing Format
UPS051/UPS052(NTSC/PAL)/CCIR656/YUV/Parallel RGB Input time chart
6.3. UPS051 Interface Timing Characteristic
(VDD=+3.0 to +3.6V, VSS=0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
CLKIN Frequency
HSD Period
fCLKIN
tH
12.5
1024
27
1716
27.19
1728
MHZ
CLKIN
HSD Display Period
tHD
960 CLKIN
HSD Back Porch
tHBP
84 100 115 CLKIN
HSD Front Porch
tHFP
14 686 718 CLKIN
HSD Pulse Width
tHSW
1
1 tHBP-1 CLKIN
VSD Period Time
tV
242.5
262.5
450.5
H
Vertical Display Area
tVD
240 H
VSD Back Porch
Odd
Even
tVBP
1 21 31
1.5
21.5
31.5
H
VSD Front Porch
Odd
Even
tVFP
1.5
1
1.5 179.5
1 179
H
VSD Pulse Width
tVSW
1
1
6H
1 Frame
485 525 901
H
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ILLUMINANT
6.4. UPS052 Interface Timing Characteristic
A. UPS052 (320mode/NTSC/24.535Mhz) Time Specifications
(VDD=+3.0 to +3.6V, VSS=0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
CLKIN Frequency
HSD Period
fCLKIN
tH
20.45
1306
24.535
1560
30
1907
MHZ
CLKIN
HSD Display Period
tHD
1280
CLKIN
HSD Back Porch
tHBP
3 241 255 CLKIN
HSD Front Porch
tHFP 25 39 372 CLKIN
HSD Pulse Width
tHSW
1
1 200 CLKIN
VSD Period Time
tV
242.5
262.5
450.5
H
Vertical Display Area
tVD
240 H
VSD Back Porch
Odd
Even
tVBP
1 21 31
1.5
21.5
31.5
H
VSD Front Porch
Odd
Even
tVFP
1.5
1
1.5 179.5
1 179
H
VSD Pulse Width
tVSW
1
1
6H
1 Frame
485 525 901
H
B. UPS052 (320mode/PAL/24.375Mhz) Time Specifications
(VDD=+3.0 to +3.6V, VSS=0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
CLKIN Frequency
HSD Period
fCLKIN
tH
20.45
1306
24.375
1560
30
1907
MHZ
CLKIN
HSD Display Period
tHD
1280
CLKIN
HSD Back Porch
tHBP
3 241 255 CLKIN
HSD Front Porch
tHFP 25 39 385 CLKIN
HSD Pulse Width
tHSW
1
1 200 CLKIN
VSD Period Time
tV
292.5
312.5
450.5
H
Vertical Display Area
tVD
288 H
VSD Back Porch
Odd
Even
tVBP
3 23 34
3.5
23.5
34.5
H
VSD Front Porch
Odd
Even
tVFP
1.5
1
1.5 128.5
1 128
H
VSD Pulse Width
tVSW
1
1
6H
1 Frame
585 625 901
H
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ILLUMINANT
C.UPS052 (360mode/NTSC/ 27Mhz) Time Specifications
(VDD=+3.0 to +3.6V, VSS=0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
CLKIN Frequency
HSD Period
fCLKIN
tH
23
1466
27
1716
30
1907
MHZ
CLKIN
HSD Display Period
tHD
1440
CLKIN
HSD Back Porch
tHBP
3 241 255 CLKIN
HSD Front Porch
tHFP 25 35 312 CLKIN
HSD Pulse Width
tHSW
1
1 200 CLKIN
VSD Period Time
tV
242.5
262.5
450.5
H
Vertical Display Area
tVD
240 H
VSD Back Porch
Odd
Even
tVBP
1 21 31
1.5
21.5
31.5
H
VSD Front Porch
Odd
Even
tVFP
1.5
1
1.5 179.5
1 179
H
VSD Pulse Width
tVSW
1
1
6H
1 Frame
485 525 901
H
D.UPS052 (360mode/PAL/ 27Mhz) Time Specifications
(VDD=+3.0 to +3.6V, VSS=0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
CLKIN Frequency
HSD Period
fCLKIN
tH
23
1466
27
1728
30
1920
MHZ
CLKIN
HSD Display Period
tHD
1440
CLKIN
HSD Back Porch
tHBP
3 241 255 CLKIN
HSD Front Porch
tHFP 25 47 255 CLKIN
HSD Pulse Width
tHSW
1
1 200 CLKIN
VSD Period Time
tV
292.5
312.5
450.5
H
Vertical Display Area
tVD
288 H
VSD Back Porch
Odd
Even
tVBP
3 23 34
3.5
23.5
34.5
H
VSD Front Porch
Odd
Even
tVFP
1.5
1
1.5 128.5
1 128
H
VSD Pulse Width
tVSW
1
1
6H
1 Frame
585 625 901
H
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ILLUMINANT
6.5. CCIR 656 Vertical Timing Characteristic
A.NTSC mode
1
0
B.PAL mode
F
EVEN Field
ODD Field
HV
EAV BLANKING
SAV ACIVE VIDEO
1
0
I2501-6IGN9624B
F
EVEN Field
ODD Field
H
EAV
SAV
18/45
V
BLANKING
ACIVE VIDEO
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ILLUMINANT
6.6. YUV720 and YVU640 Input Timing
A.YUV720 mode(NTSC Input Timing)
Parameter
CLKIN Frequency
HSD Period
HSD Display Period
HSD Back Porch
HSD Front Porch
HSD Pulse Width
VSD Period Time
Vertical Display Area
VSD Back Porch
VSD Front Porch
VSD Pulse Width
1 Frame
Odd
Even
Odd
Even
Symbol
fCLKIN
tH
tHD
tHBP
tHFP
tHSW
tV
tVD
tVBP
tVFP
tVSW
Min.
--
--
--
--
--
--
--
--
--
--
--
--
Typ.
27
1716
1440
240
36
1
262.5
240
21
21.5
1.5
1
1
525
Max.
--
--
--
--
--
--
--
--
--
--
--
--
Unit
MHZ
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
H
H
H
H
H
H
B.YUV720 mode(PAL Input Timing)
Parameter
CLKIN Frequency
HSD Period
HSD Display Period
HSD Back Porch
HSD Front Porch
HSD Pulse Width
VSD Period Time
Vertical Display Area
VSD Back Porch
VSD Front Porch
VSD Pulse Width
1 Frame
Odd
Even
Odd
Even
Symbol
fCLKIN
tH
tHD
tHBP
tHFP
tHSW
tV
tVD
tVBP
tVFP
tVSW
Min.
--
--
--
--
--
--
--
--
--
--
--
--
Typ.
27
1728
1440
240
48
1
312.5
288
24
24.5
0.5
0
1
625
Max.
--
--
--
--
--
--
--
--
--
--
--
--
Unit
MHZ
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
H
H
H
H
H
H
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ILLUMINANT
C.YUV640 mode(NTSC Input Timing)
Parameter
CLKIN Frequency
HSD Period
HSD Display Period
HSD Back Porch
HSD Front Porch
HSD Pulse Width
VSD Period Time
Vertical Display Area
VSD Back Porch
VSD Front Porch
VSD Pulse Width
1 Frame
Odd
Even
Odd
Even
Symbol
fCLKIN
tH
tHD
tHBP
tHFP
tHSW
tV
tVD
tVBP
tVFP
tVSW
Min.
--
--
--
--
--
--
--
--
--
--
--
--
Typ.
24.535
1560
1280
240
40
1
262.5
240
21
21.5
1.5
1
1
525
Max.
--
--
--
--
--
--
--
--
--
--
--
--
Unit
MHZ
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
H
H
H
H
H
H
D.YUV640 mode(PAL Input Timing)
Parameter
CLKIN Frequency
HSD Period
HSD Display Period
HSD Back Porch
HSD Front Porch
HSD Pulse Width
VSD Period Time
Vertical Display Area
VSD Back Porch
VSD Front Porch
VSD Pulse Width
1 Frame
Odd
Even
Odd
Even
Symbol
fCLKIN
tH
tHD
tHBP
tHFP
tHSW
tV
tVD
tVBP
tVFP
tVSW
Min.
--
--
--
--
--
--
--
--
--
--
--
--
Typ.
24.375
1560
1280
240
40
1
312.5
288
24
24.5
0.5
0
1
625
Max.
--
--
--
--
--
--
--
--
--
--
--
--
Unit
MHZ
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
H
H
H
H
H
H
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ILLUMINANT
6.7. Parallel RGB Input Timing
Parameter
CLKIN Frequency
HSD Period
HSD Display Period
HSD Back Porch
HSD Front Porch
HSD Pulse Width
VSD Period Time
Vertical Display Area
VSD Back Porch
VSD Front Porch
VSD Pulse Width
1 Frame
Odd
Even
Odd
Even
Symbol
fCLKIN
tH
tHD
tHBP
tHFP
tHSW
tV
tVD
tVBP
tVFP
tVSW
6.8. Data Input Format
A .UPS051/UPS052/YUV Mode
Min.
--
--
40
--
--
--
--
--
--
--
--
--
Typ.
6,2
390
320
61
9
1
262.5
240
21
21.5
1.5
1
1
525
Max.
7,5
--
--
--
--
--
--
--
--
--
--
--
Unit
MHZ
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
H
H
H
H
H
H
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ILLUMINANT
B. Parallel RGB Mode
C.CCIR MODE
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ILLUMINANT
6.9. Internal Register Description
The 3-wire CPU serial interface is used and set to the data writing in these internal
registers. Each serial command consists of 16 bits of data that is loaded one bit a time at the
rising edge of serial clock SPCK. Command loading operation starts from the falling edge of
SPENB and is completed at the next rising edge of SPENB
3 Wire Serial Command Format
Serial Control Timing
Item
SPENB Input Setup Time
Serial Data Input Setup Time
SPENB Input Hold Time
Serial Data Input Hold Time
SPCK Pulse High Width
SPCK Pulse Low Width
SPENB Pulse High Width
I2501-6IGN9624B
Symbol
tS0
tS1
tH0
tH1
tWH1
tWL1
tW2
Min.
50
50
50
50
50
50
400
Typ.
--
--
--
--
--
--
--
Max.
--
--
--
--
--
--
--
Unit
ns
ns
ns
ns
ns
ns
ns
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ILLUMINANT
Register Summary
3-Wire Register Table
Notes:
1. When RSTB is low, all registers reset to default values.
2. Serial Commands are executed at next VSD signal.
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ILLUMINANT
Register Description (3 wire)
R0-Vcom_AC(R0[3:0]:Common Voltage AC Level Selection
Register
R0
Register Address
A6 R/W A5 A4 A3 A2 A1
0 0 0 000 0
Register Data (Default)
A0 D7
D6 D5 D4 D3 D2 D1
0
Y-CbCr CCIR601
(0) (0)
X
X
VCOM_AC
(0110)
D0
D3 D2 D1 D0 Voltage(V)
00 0 0
3.6
00 0 1
3.7
00 1 0
3.8
00 1 1
3.9
01 0 0
4.0
01 0 1
4.1
0 1 1 0 4.2(Default)
01 1 1
4.3
10 0 0
4.4
10 0 1
4.5
10 1 0
4.6
10 1 1
4.7
10 XX
4.8
Note : The default value will change by VCOMDC trim function
R0-CCIR601(R0[6]) : CCIR601 input timing selection
CCIR601
Function
0 Disable CCIR601 (Default)
1 Enable CCIR601 (Please refer to the table of R4(SEL) for detail description
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ILLUMINANT
R0-Y_CbCr(R0[7])
Y&CbCr exchange position (only valid for 8-bit input YUV640/YUV720)
R1-VCOM_DC(R1[5:0]) : Common voltage DC level selection (20Mv/step)
D5~D0
00h
:
21h
:
3Fh
VCOM DC Level
0.24
:
0.90 (Default)
:
1.5
Note : The default value will change by VCOMDC trim function
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ILLUMINANT
R1-VCDCE(R1[7]) : VCOM_DC enable control
D7 VCDCE Function
0 VCOM_DC Function Disabled. The VCOMDC pin is disabled.
1 VCOM_DC Function Enabled. The VCOMDC voltage follows VCOM_DC setting
R3-Brightness(R3[7:0])
Setting Accuracy 1Bit/Step
D7~D0
Brightness Gain
00h Dark. (-64)
40h Center(0). (Default)
FFh Bright. (+191)
R4-HDIR(R4[0]) : Shift registers of source driver direction selection
D0 HDIR Function
0 Shift from right to left. Y0<-Y1<-……<-Y959<-Y960
1 Shift from right to left. Y0->Y1->……->Y959->y960 (Default)
R4-VDIR (R4[1]) : Gate driver output direction selection
D1 VCDCE Function
0 Shift from down to up. L0<-L1<-……<-L239<-L240
1 Shift from up to down. L0->L1->……->L2440->L240 (Default)
R4-NTSC/PAL (R4[3:2]) : NTSC or PAL input mode selection
D3 D2 NTSC/PAL Mode
0 0 PAL.
0 1 NTSC.
1 X Auto Detection. (Default)
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ILLUMINANT
R4-SEL (R4[5:4]) : Input data timing format selection
CCIR601 YUV
SEL
D5 D4
Input Timing Format
0 0 0 0 8-bit RGB. (Default)
0 0 0 1 8-bit Dummy RGB 320X240.
0 0 1 X 8-bit Dummy RGB 360X240.
0 1 X X CCIR656
1 1 0 X YUV640
1 1 1 0 YUV720
R4-YUV (R4[6]) : YUV(CCIR656) or RGB input selection
D6 Data Format
0 RGB input. (Default)
1 CCIR656 / YUV640 / YUV720 input.
R4-Narrow (R4[7]) : Normal Display and Narrow Display selection
D7 Function
0 Normal display. (Default)
1 Narrow display.
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ILLUMINANT
R5-STB (R5[0]) : Standby (Power Saving) Mode
D0 STB Function
0 Standby Mode. (Default)
1 Normal Operation
Note : In standby mode, source driver output. VGH, VGL, and FRP are all 0V.
R5-SHDB1 (R5[1]) : Shut down for bank light power converter
D1 SHDB1 Function
0 The back light power converter is off
1 The back light power converter is controlled by STB’s power sequence (Default)
R5-SHDB2 (R5[2]) : Shut down for VGH/VGL charge pump
D1 SHDB2 Function
0 VGH/VGL charge pump is always off
1 VGH/VGL charge pump is controlled by STB’s power On/Off sequence. (Default)
R5-PWM_DUTY (R5[5:3]) : PWM duty cycle selection for back light power
convert
SHDB1 Function
Function
D5 D4 D3
PWM duty cycle
000
55%
001
60%
010
65%
011
70%(Default)
100
75%
101
80%
110
85%
111
90%
R5-PWM_DUTY (R5[6]) : Global Reset
D6 GRB Function
0 Reset all registers to default value
1 Normal operation. (Default)
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ILLUMINANT
R5-DRV_FREQ (R5[7]) : DRV signal frequency setting
D7 DRV Frequency
0 CLKIN/64. (Default)
1 CLKIN/128
R6-VBLK (R6[4:0])
Vertical blanking setting for 8-bit RGB, 8-bit Dummy RGB&CCIR656
For 8-bit RGB, 8-bit Dummy RGB, CCIR656, YUV640 and YUV720 NTSC mode,
Parallel RGB input mode (PSEL=”LOW”).
D4~D0
VBLK Function
Unit
00h~03h 3.
04h 4.
15h 31. (Default)
H
1Fh 31
For 8-bit Dummy RGB,CCIR656,YUV640 and YUV720 PAL mode.(Vertical blanking+3)
D4~D0
VBLK Function
Unit
00h 3.
15h 24. (Default)
H
1Fh 34
R6—LED_CURRENT (R6[6:5]): LED current adjustable for DC-DC feedback
threshold voltage
D6~D5
VBLK Function
00 0.6V. (Default)
01 0.75V
10 0.45V
11 0.3V
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