Illuminant
Illuminant


I2420-6OMN4823A

LCM


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ILLUMINANT 北極光企業有限公司
PRODUCT SPECIFICATION FOR LCM
CUSTOMER:
MODEL NO:
I2420-6OMN4823A
ACCEPTED BY:
APPROVED BY: CHECKED BY: ORGANIZED BY:
2008.08.25
lLong
2008.08.25
Vicky
2008.08.25
Vicky
Approval for Specifications Only
Approval for Specifications and Sample
Note: 1. Version of Specifications : 1
2. Others: Rohs Compliment
TAIWAN
1F, #15, LANE 75, MIN CHUAN E. RD., SEC 3, TAIPEI, TAIWAN.
Tel +886-2-25175115 Fax +886-2-25175099
CHINA
5F DONGWU COMMERICAL BLDG., LANSHAN RD., NORTH DISTRICT, HI-TECH INDUSTRIAL PARK, SHENZHEN, PRC.
TEL + 86-755-86154466 FAX +86-755-86154366
KOREA
RM 1201, IT MIRAE TOWER, 60-21, GASAN-DONG, GEUMCHEON-GU, SEOUL, 153-801, KOREA
TEL + 82-2-2027-5391~2 FAX +82-2-2027-5393
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ILLUMINANT
Version
1
Date
08/08/25
Contents
Initial Release
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ILLUMINANT
CONTENTS
1. Mechanical Specification
2. Absolute Maximum Ratings
3. Electrical Characteristics
4. Optical Characteristics
5. Interface
6. AC Characteristics
7. Power On/Off Sequence
8. Block Diagram
9. Backlight
10. Reliability
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ILLUMINANT
1. Mechanical Specification
Item
Display Size
Module Dimension
Active Area
Number of Dots
Pixel Pitch
LCD Type
Viewing Direction
Approx. Weight
Various Color Display
Brightness
Backlight Type
Backlight Color
Standard Value
2.36
55.20(W)*47.55(H)*2.90(D)
48.0(W)*35.69(H)
480(RGB)*234 Delta Type
0.1(W)mm*0.1525(H)
Normal White
6H
TBD
16.7M
250
1-LED parallel
White
Unit
inch
mm
mm
Dot
mm
-
-
g
cd/m2
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ILLUMINANT
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ILLUMINANT
2. Absolute Maximum Ratings
Item
Supply Voltage for Logic
Input Voltage
Operating Temperature
Storage Temperature
*NOTE: Based on Vss=0V.
Symbol
VDD
Vin
TOP
TST
Min.
-0.5
-0.3
0
-25
Typ. Max. Unit Remark
+7.0 V
VDD+0.3 V
- +60
-
- +80
-
3. Electrical Characteristics
Item
Supply Voltage
Supply
Voltage for
Gate Driver
Digital
Input
Voltage
Digital
Output
Voltage
H Level
L Level
H Level
L Level
H Level
L Level
VCOM
Symbol
VDD
VDDIO
VGH
VGL
VIH
VIL
VOH
VOL
Min.
3.0
Values
Typ.
3.3
Max.
3.6
3.0 3.3 3.6
17 18.5 19.5
-7.5 -6 -4.5
VDDIO-0.4- -
VDDIO
0 - VDDIO+0.4
0.7VDDIO -
VDDIO
0 - 0.3VDDIO
VLCOMAC - +4.5 +5.0
VLCOMDC - 0.72 -
Unit Remark
V
Note 3-1
V Note 3-1
V
V
V
V
V
Vp-p
V
AC
Component
of VCOM
Note 3-2
Note 3-1 : VGH and VGL supplied by internal setup circuit.
Note 3-2 : Adjust VCDC to make the flicker level be minimum. Suggest R5 setting data 0x7d.
Current Consumption
Parameter
Supply
Current
Symbol
IDD
Condition
VDD=+3.3V
Typ.
9
Max.
13.2
Unit Remark
mA -
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ILLUMINANT
4. Optical Characteristics
The following items are measured under stable conditions. The optical characteristics
should be measured in a dark room or equivalent state with the methods shown in
Note1,2,3.
Item
Response Time
Contrast Ratio
Viewing
Angle
Hor.
Ver.
Transmission
White Chromaticity
Shift
Brightness
Symbol
TR
TF
CR
R
L
H
L
YL
X
Y
Condition
ࣂ =0
At optimized
viewing
angle
CR10
ࣂ =0
ࣂ =0
ࣂ =0
Min
-
-
-
40
40
10
30
-
0.26
0.28
200
Typ Max Unit Remark
6
15
12
30
ms
ms
Note 4,6
400 -
- Note 5,6
45 -
45
15
-
-
Degree Note 6,7
35 -
6.5 -
% Note 8
0.31 0.36
0.33 0.38
-
250 - Cd/m2
Note 1 : Ambient temperature =25
Note 2 : To be measured in the dark room.
Note 3 : To be measured on the center area of panel with a field angle of 1by Topcon luminance
meter BM-7, after 10minutes operation.
Note 4 : Definition of Response time
The output signals of photo detector are measured when the input signals are changed from
“ black” to “white” (falling time) and from “white” to “black” (rising time), respectively.
The response time is defined as the time interval between the 10% and 90% of amplitudes.
Refer to figure as below.
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ILLUMINANT
Note 5 : Definition of Contrast Ratio
Contrast Ratio is calculated with the following formula.
Contrast Ratio (CR) =
Brightness measured when LCD is at “white state”
Brightness measured when LCD is at “black state”
Note 6 : White Vi=Viso -/+1.5V
Black Vi=Viso ± 2.0V
“±”means that the analog input signal swings in phase with COM signal.
“-/+” means that the analog input signal swings out of phase with COM signal.
Vsio : The analog input voltage when transmission of LCD panel when all the input
terminals of module are electrically opened.
Note 7 : Definition of Viewing Angle
Refer to the figure as below.
Note 8 : Measured at the center area of the panel when all the input terminals of LCD panel
are electrically opened.
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ILLUMINANT
5. Interface
Pin Symbol I/O
Function
1 VCOM I Common Electrode Driving Voltage
Remark
Note 5-1
2 NC -- -
3 VGL O Power Supply for Gate off Voltage
4
C4P
C
Pins to Connect Capacitance for Power
Circuitry
5
C4N
C
Pins to Connect Capacitance for Power
Circuitry
6 VGH O Power Supply for Gate on Voltage
7 FRP O Frame Polarity Output for VCOM
8
VCAC
O
Define the Amplitude of the VCOM
swing
Intermediate Voltage for Charge Pump.
9 VDD_25V O Please Connect the Capacitor between
VDD_25V and VSS
10 C3P
C
Pins to Connect Capacitance for Power
Circuitry
11 C3N
C
Pins to Connect Capacitance for Power
Circuitry
Note 5-2
Charge-pump Circuit Reference Voltage.
12 VDD3 O Please connect the Capacitor between
VCIOUT and VSS
13 C2P
C
Pins to Connect Capacitance for Power
Circuitry
14 C2N
C
Pins to Connect Capacitance for Power
Circuitry
Power Supply Voltage of Source Driver
15 VDDA
O
Liquid Crystal Drive Circuit.
Please Connect the Capacitor between
DDVDH and VSS.
16 C1P
C
Pins to Connect Capacitance for Power
Circuitry
17 C1N
C
Pins to Connect Capacitance for Power
Circuitry
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ILLUMINANT
18 GND
19 VDD
20 DRV
21 VLED
P Charge Pump Power GND
P Charge Pump Power VDD
O
Gate Signal for the Power Transistor of
the Boost Converter
P Supply Voltage for LED Backlight
Note 5-3
Note 5-4
22 NC
-- Dummy
23 FB
I Main Boost Regulator Feedback Input Note 5-5
24 NC
-- Dummy
25 AGND
26 VDDIO
27 CSB
P Ground Terminal in the Logic Circuit
P
Power Supply Terminal in the Logic
Circuit
I Serial Communication Chip Select
Note 5-3
28 SDA I/O Serial Communication Data Input
29 SCL
I Serial Communication Clock Input
30 HSYNC I Horizontal Sync Input
Note 5-6
31 VSYNC I Vertical Sync Input
Note 5-7
32 DCLK
I Clock Input
Note 5-8
33 D7
I Data Input : MSB
34 D6
I Data Input
35 D5
I Data Input
36 D4
I Data Input
37 D3
I Data Input
38 D2
I Data Input
39 D1
I Data Input
40 D0
I Data Input
I : Input O: Output P : Power I/O : Serial Communication Data Input/Output C : Capacitor
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ILLUMINANT
Note 5-1 : VCOM=+5.0 Vp-p.(Typ.)
Note 5-2 : The external capacitor is required on those pins as following.
Symbol
VDD3
VDDA
VGH
VGL
VCAC
C1P, C1N
C2P, C2N
C3P, C3N
C4P, C4N
FRP
VDD_25V
Part Standard
Capacitance
Voltage
1 to 2.2uF
16V over
1 to 2.2uF
16V over
1 to 2.2uF
25V over
1 to 2.2uF
25V over
1 to 2.2uF
16V over
1 to 4.7uF
16V over
1 to 4.7uF
16V over
1 to 4.7uF
16V over
1 to 4.7uF
16V over
1 to 2.2uF
16V over
1 to 2.2uF
16V over
Notes
Note 5-3 : VDD, VDDIO=+3.3V(Typ.)
Note 5-4 : Outputs the control signal of switching regulator for LED, Duty cycle
varies according to FB input voltage.
Note 5-5 : Feedback signal of switching for LED, It controls DRV output duty cycle
with 0.6V input level sense.
Note 5-6 : Horizontal sync signal, it is a “L” active signal.
Note 5-7 : Vertical Sync signal, it is a “Low” active signal.
Note 5-8 : Dot clock signal for RGB interface, timing for data loading defined
at rising edge.
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ILLUMINANT
6. AC Characteristics
AC Characteristics (VDD=3.3V, AND=GND=0V, TOPR=-30to =85)
Parameter
CLK pulse duty
Delay between Hsync and DCLK
Hsync width
Hsync period
Vsync setup time
Vsync hold time
Hsync set-up time
Hsync hold time
Data set-up time
Data hold time
Vsync to 1st gate output
CCIR V to 1st gate output
CCIR V to 1st gate output
SD output stable time
GD output delay time
GD output rise and fall time
Serial communication
Serial clock period
Serial clock duty cycle
Serial clock width low/high
Serial data setup time
Serial data hold time
CSB setup time
CSB data hold time
Chip select distinguish
Delay between CSB and Vsync
Symbol
TCW
Thc
Twh
Th
Tvst
Tvhd
Thst
Thhd
Tdsu
Tdhd
Tstv
Tstv
Tstv
Tst
Tgd
Tgst
Conditions
D00~D07 to DCLK
D00~D07 to DCLK
Sel”111”;By HDL[3..0] settings
Sel=”111” NTCS (PAL=0);
By HDL[3..0] settings
Sel=”111” PAL=1;
By HDL[3..0] settings
30mV precision; CL=6.75pF,
R=3.62K
CL=17.6pF, R=1.29K
CL=17.6pF, R=1.29K
10% to 90%
Min. Typ. Max. Unit
40 50 60
%
- - 1.0 DCLK
1.0 -
- DCLK
60 63.56 67
us
12 - - ns
12 - - ns
12 - - ns
12 - - ns
12 - - ns
12 - - ns
6 13 21 Th
14 21 29 Th
20 27 35 Th
- 25 30 us
- 900 1500 ns
- 900 1500 ns
Tsck
Tscw
Tssw
Tist
Tihd
Tcst
Tchd
Tcd
Tcv
320 -
40 50
120
120
120
120
120
1
1
-
60
ns
%
ns
ns
ns
ns
ns
us
us
6.1. Raw Data Mode
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ILLUMINANT
(VDDIO=1.8V~VDD, VDD=+3.0 to +3.6V, VSS=0V)
Parameter
DCLK frequency
DCLK period
Delay from Hsync to Source Output
Delay from Hsync to Gate Output
Delay from Hsync to Gate Output off
Delay from Hsync to Q1H
Delay from Hsync to FRP
Delay from Hsync to 1st data input
DC converter osc. Frequency
Symbol
Fclk
Tcph
Thso
Thgo
Thgz
Thq
Thf
Ths
Fosc
Conditions
Function of DDL[5..0] settings
Fclk/32
Min.
-
-
-
-
-
-
68
-
Typ.
9.7
103
56
45
19
39
59
100
303.1
Max.
-
-
-
-
-
-
-
131
-
Unit
MHz
Ns
DCLK
DCLK
DCLK
DCLK
DCLK
DCLK
KHz
6.2. Serial RGB Mode
A. 360 Mode (27Mhz) Time Specifications
B. 320 Mode (24.545Mhz) Time Specifications
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ILLUMINANT
(VDDIO=1.8V~VDD, VDD=+3.0 to +3.6V, VSS=0V)
Parameter
DCLK frequency
DCLK cycle time
Delay from Hsync to Source Output
Delay from Hsync to Gate Output
Delay from Hsync to Gate Output off
Delay from Hsync to Q1H
Delay from Hsync to FRP
Delay from Hsync to 1st data input
DC converter osc. Frequency
Symbol
Fclk
Conditions
Tcph
Thso
Thgo
Thgz
Thq
Thf
Ths Function of DDL[5..0] settings
Fosc Fclk/64=383.4kHz /421.9kHz
Min.
-
-
Typ.
24.54/
27
40/37
Max.
-
-
Unit
MHz
ns
- 143 - DCLK
- 113 - DCLK
- 48 - DCLK
- 100 - DCLK
143 DCLK
220 252 283 DCLK
383.4/
421.9
KHz
6.3 CCIR Mode (CCIR 656)
Timing Characteristic
(VDDIO=1.8V~VDD, VDD=+3.0 to +3.6V, VSS=0V)
Parameter
DCLK frequency
DCLK cycle time
CLK pulse duty
Delay from EAV to Source Output
Delay from EAV to Gate Output
Delay from EAV to Gate Output off
Delay from EAV to Q1H
Delay from EAV to FRP
Delay from EAV to 1st data input
DC converter osc. Frequency
Symbol
Fclk
Tcph
Tcw
Thso
Thgo
Thgz
Thq
Thf
Ths
Fosc
Conditions
Function of DDL[5..0] settings
Fclk/64
Min.
-
-
40
-
-
-
-
241
Typ.
27
37
50
143
113
48
100
143
273
421.9
Max.
-
-
60
-
-
-
-
304
Unit
MHz
ns
%
DCLK
DCLK
DCLK
DCLK
DCLK
DCLK
KHz
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ILLUMINANT
6.4 Internal Register Description
There is a total of 16 registers each containing several parameters. For a detailed description of the
parameters refer the Register summary.
The serial register has read (1) / write (0) function. D [15:12] are the register address, D [11] defined the
read or write mode and D [10:0] are the data. Register 14 is a read only register and is used for chip
identification. At power-on, the default values specified for each parameter (in Register summary)
are taken. All data, except S0 D[3:2], are validated on the negative edge of Vsync. In 3-wire register, GRB
clear registers to default value except GRB value. If less than 16-bit data are read during the CS low time
period the data is cancelled.
Register Summary
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ILLUMINANT
Register Description
S0 Settings
R0: System settings
Adress
0000
Bit
[3:0]
Bit3(GRB)
Bit2(STB)
Bit1(SHDB)
Bit0(SHCB)
Description
Global reset
Standby mode setting
DC-DC converter shutdown setting
Charge Pump shutdown setting
Default
xxxx_1101b
Bit3 GRB Function
0
The controller is resets, the charge pump and DC-DC is off.
Reset all register to default value.
1 Normal operation. (Default)
Bit2 STB Function
0 T-CON, source driver and DC-DC converter are off. All outputs are High-Z.
1 Normal operation. (Default)
Bit1 SHDB Function
0 DC-DC converter is off. (Default)
1
DC-DC converter is on.
DC-DC controls by STB and power on/off sequence.
Bit0 SHCB Function
0 Charge Pump converter is off.
1
Charge Pump converter is on. (Default)
Charge Pump controls by STB and power on/off sequence.
S1 Settings
Adress
0001
Bit
[7:0]
Bit[7:5](GAMAH)
Bit[4:3](PDTY)
Bit[2:0](FBV)
Description
Internal GAMAH voltage generator setting for Gamma
PWM1 duty control for DC2DC converter
FB1 reference level adjustment for DC2DC converter
Default
0110_0100b
Bit[7:5]
000
001
010
011
100
101
110
111
GAMAH Level
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
Unit
V
Bit[4:3]
00
01
10
11
PTDY Duty
75
55
60
65
Unit
%
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ILLUMINANT
Bit[2:0]
000
001
010
011
100
101
110
111
FB Vref Level
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
Unit
V
S2 Settings
Adress Bit
0010 [5:0] Bit2(DITH)
Description
Dithering algorithm selection
Bit2 DITHB Function
0 Dithering on. 8-bit resolution. (Default)
1 Dithering off. 6-bit resolution (last 2bits of input data truncated)
Bit1
0 PFON=”L”, Pre-filter off
PFON Function
1
PFON=”H”, Pre-filter on
Remark : Disable this function In RAW DATA MODE mode
Default
xx00_0001b
S3 Settings
Adress
0011
Bit
[3:0]
Bit[3:0](CONST)
Description
RGB constant level adjustment (0.125/Step)
Bit[3:0]
0x0
0x8
0xF
RGB constrast
0
1.00
1.875
Default
x000_1000b
S4 Settings
Adress Bit
0011 [3:0] Bit3(FPOL)
Bit1(UD)
Bit0(SHL)
Description
FRP source driver polarity inversion polarity inversion
selection
Vertical shift direction selection
Horizontal shift direction selection
Default
xxxx_0011b
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ILLUMINANT
Bit3 FPOL Function
0
FRP=0 when positive polarity
FRP=1 when negative polarity (Default)
1
FRP=0 when positive polarity
FRP=1 when negative polarity
Bit1 UD Function
0 Scan down : First line=G241=>G240=>…=>G1=>Last line=G0
1 Scan up : First line=G0=>G1=>…=>G240=>Last line=G241 (Default)
Bit0 SHL Function
0 Shift left; First data=S480=>S479=>…=>S2=>Last data=S1
1 Shift right; First data=S1=>S2=>…=>S479=>Last data=S480 (Default)
S5 Settings
Adress
0101
Bit Description
[6:0] Bit6(VDCEN)
Setting FRP output to add DC level
Bit[5:0](VCOMDC) VCOM DC Level adjustment
Default
x010_0000b
Bit6 VDCEN Function
0 VDCEN=”L”, without VCOM DC Level
1 VDCEN=”H”, with VCOM DC Level
Bit[5:0]
0x0
0x20
0x3F
VCOMDC Setting Table
0.192
0.704
1.2
Unit
V
Note : S5 setting step must be enter the test mode, then start set the S5 register and data.
Interval VCOMDC voltage can adjust by the S5 data.
S6 Settings
Adress
0110
Bit
[4:0]
Bit4(PALM)
Bit3(PAL)
Bit[2:0] (SEL)
Description
Select skip method in PAL mode interface
PAL/NTSC selection
Select Raw data/SERIAL RGB MODE path and
input data format
When SEL[2:0] select different, AC timing also
different.
Bit4 PALM Function
0 PAL 280 active lines. (Default)
1 PAL 280 active lines.
Default
xxx0_0000b
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ILLUMINANT
Bit3 PAL Function
0 NTSC Input format (240 active line). (Default)
1 PAL Input format.
Bit[2:0]
000
001
010
111
SEL Function
Select RAW DATA MODE path, special data
format(DDX) input
Select SERIAL MODE path, normal data
format(DIN) input
Select SERIAL MODE path, normal data
format(DIN) input
Select CCIR_656 path, format(YcbCr) input.
Operating Frequency
9.7MHz
24.54MHz
27MHz
27MHz
S7 Settings
Adress
0111
Bit
[6:0] Bit[6:0](BRADJ)
Description
Brightness Level Adjustment
Bit[6:0]
0x00
0x40
0x7F
Brightness Level
-256
0
+256
S8 Settings
Adress
1000
Bit
[4:0] Bit[4:0](DDL)
Bit[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
Description
Horizontal Data start delay selection
DDL Function
No.
0
+1
+2
+3
+4
+5
+6
+7
+8
+9
+10
+11
+12
+13
+14
+15
-1
-2
-3
-4
I2420-6OMN4823A
19/28
Default
x100_0000b
Default
xxx0_0000b
Unit
DCLK
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ILLUMINANT
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-16
S10 Settings
Adress Bit
1010 [5:0]
Bit[5:4](FRAD)
Bit[3:0](HDL)
Description
Odd frame or Even frame advance select
Select the Data delay timing
Bit[5:4]
00
01
10
FRAD Function
Odd/Even frame Tstv are the same
Even frame Tstv=HDL setting+1, unit=H
Odd frame Tstv=HDL setting+1, unit=H
Remark: This function is enable in SEL[2:0]=”111”mode
S12 Settings
Adress Bit
1100 [2:0]
Bit[2:0](VCSL)
Bit[2:0]
000
001
010
011
100
101
110
111
Description
VCAC Level Selection
VCAC Level
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
Default
xx00_0000b
Default
xxxx_x101b
Unit
V
S14 Settings
Adress Bit
1110 [4:0]
Bit4(GAMSEL)
Bit4
0
1
Description
Gamma R Table selection
GAMSEL Function
GAMSEL=”L” select GAM1 value
GAMSEL=”H” select GAM2 value
I2420-6OMN4823A
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Default
xxx0_0011b
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ILLUMINANT
6.5 CPU Serial Transfer Timing Wave Form :
The register setting is done by 3-interface of chip select signal (CS_X), serial clock
signal (SCL), and data input signal (SDA) from CPU etc.
When CS_X=L, it is recognized forwarding to this chip, and takes the SDA signal
by rising edge about the SCL signal. The forwarding ends with CS_X=H and only the
data of the register corresponding to LSI holds. The forwarding bits is 16-bits and
3bits of the head becomes an address cord and 13 bits after those becomes register
setting data. It is forwarded to the turn of LSB from MSB.
If less than 16-bits of SCL are input while CS_X=L, the transferred data is ignored.
If 16-bits or more of SCL are input while CS_X=L, the first 16-bits of transferred
data before the rising edge of CS_X pulse are valid data.
After power-on reset is released, the command of the initial operation setting etc.
can be forwarded. The register setting can be received in the standby mode.
(VDD=+3.0 to +3.6V, VSS=0V)
Serial Communication
Serial clock period
Serial clock duty cycle
Serial clock width low/high
Serial data setup time
Serial data hold time
CSB setup time
CSB data hold time
Chip select distinguish
Delay between CSB and Vsync
Tsck
Tscw
Tssw
Tist
Tihd
Tcst
Tchd
Tcd
Tcv
320 -
- ns
40 50 60 %
120 ns
120 ns
120 ns
120 ns
120 ns
1 us
1 us
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ILLUMINANT
7. Power On/Off Sequence
Special care should be taken that the large current may cause a permanent damage
to the LSI when voltage is applied to the LCD drive power supply terminals in the
condition that the logic power supply terminals are floating.
The following sequences are recommended from the power supply ON to the image
display.
Note
1. The software reset command by the GRB register is not cared about even if it doesn’t send it
because the initialization operation is done with LSI internal power-on reset circuit when the power
supply is turned on.
2. The setting of SHDB register and GRB register is sent at the same time and not cared about.
However, LED is lighted after the image data over 3 frames is received.
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ILLUMINANT
The following sequences are recommended from the image display to the power
supply OFF.
Note
If the SHDB register is not set as 0 before stopping image data (DOTCLK), since the transistor of
an external backlight LED control circuit may become being in ON state with as and may generate
heat, please be sure to set SHDB as 0.
RGB
GBR
2.36”TFT 480(RGB) x 234
60 1
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1
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ILLUMINANT
8. Block Diagram
8.1 Display Color and Gray Scale Reference
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ILLUMINANT
8.2 Reference Application Note
Note
1. When use the internal VcomDC adjust, the resistors R1’R2’R3 must be open.
2. When backlight is turn off, the power supply for backlight driver must be open.
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ILLUMINANT
8.3 Pixel Arrangement and Input Pin Connector No.
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ILLUMINANT
9. Backlight
9.1 Standard Lamp Styles (Edge Lighting Type):
The LED chips are distributed over the edge light area of the illumination unit, which
gives the less power consumption:
9.2 The Main Advantages of the LED Backlight are as Following:
The brightness of the backlight can simply be adjusted.
By a resistor or a potentiometer.
9.3 Data About LED Backlight:
Item
Power
Consumption
LED Current
LCM Brightness
Symbol Min.
VLED 2.8
IF -
200
Values
Typ. Max.
- 3.8
25 -
250 -
Unit
V
mA
Cd/m2
Remark
NOTE:
1.Test Instrument : BM-7 (Distance=500mm ; Field =1°)
2.Light Source : LED * 1(White)
3.Conditions : IF=25mA, VLED(Typ.)=3.3V
4.Uniformity : (Min. Brightness / Max. Brightness) *100%
5.Uniformity 70%
9.4 Measured Method:
P1 P2
P3
P4 P5
P6
P7 P8
P9
(Effective spatial Distribution)
Hole Diameter±1ø ; 1 to 9per Position Measured Luminous
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ILLUMINANT
10. Reliability
10.1 MTTF
The LCD module shall be designed to meet a minimum MTTF value of 50,000 hours with
normal condition. (25°C in the room without sunlight; not include lifetime of backlight).
10.2 Tests
No. Item
1 High Temperature Operating
2 Low Temperature Operating
3 High Temperature Non-Operating
4 Low Temperature Non-Operating
5 High Temperature /
Humidity Non-Operating
6 Temperature Shock Operating
7 Electro-Static Discharge
Condition
+60°C 240hrs
0°C 240hrs
+80°C 240hrs
-25°C 240hrs
60°C ; 90%RH ; 240hrs
Criterion
No defect of
operational function in
room temperature are
allowable(23±5°C).
Leakage current
should be below double
of initial value.
-30°C
80°C
(30min) (5min) (30min)
100 Cycles
HBM : ±2kv
Note 1: Test after 24 hours in room temperature(23±5°C).
Note 2: The sampling above is individually for each reliability testing condition.
Note 3: The color fading of polarizing filter should not care.
Note 4: All of the reliability testing chamber above, is using D.I. water.(Min value:1.0 M-cm)
Note 5: In case of malfunction defect caused by ESD damage, if it would be recovered to normal
state after resetting, it would be judged as a good part.
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