6.5 CPU Serial Transfer Timing Wave Form :
The register setting is done by 3-interface of chip select signal (CS_X), serial clock
signal (SCL), and data input signal (SDA) from CPU etc.
When CS_X=L, it is recognized forwarding to this chip, and takes the SDA signal
by rising edge about the SCL signal. The forwarding ends with CS_X=H and only the
data of the register corresponding to LSI holds. The forwarding bits is 16-bits and
3bits of the head becomes an address cord and 13 bits after those becomes register
setting data. It is forwarded to the turn of LSB from MSB.
If less than 16-bits of SCL are input while CS_X=L, the transferred data is ignored.
If 16-bits or more of SCL are input while CS_X=L, the first 16-bits of transferred
data before the rising edge of CS_X pulse are valid data.
After power-on reset is released, the command of the initial operation setting etc.
can be forwarded. The register setting can be received in the standby mode.
(VDD=+3.0 to +3.6V, VSS=0V)
Serial clock period
Serial clock duty cycle
Serial clock width low/high
Serial data setup time
Serial data hold time
CSB setup time
CSB data hold time
Chip select distinguish
Delay between CSB and Vsync
40 50 60 %
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