NXP Semiconductors Electronic Components Datasheet



ADC0804S030

(ADC0804S030 - ADC0804S050) Single 8 bits ADC


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ADC0804S030/040/050
www.DataSheet4U.com
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Rev. 02 — 14 August 2008
Product data sheet
1. General description
The ADC0806030/040/050 are a family of 8-bit high-speed, low-power Analog-to-Digital
Converters (ADC) for professional video and other applications. It converts the analog
input signal into 8-bit binary coded digital signals at a maximum sampling rate of 50 MHz.
All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible,
although a low-level sine wave clock input signal can also be used.
The device requires an external source to drive its reference ladder. If the application
requires that the reference is driven via internal sources, NXP recommends you use one
of the ADC1003S030/040/050 family.
2. Features
I 8-bit resolution
I Sampling rate up to 50 MHz
I DC sampling allowed
I One clock cycle conversion only
I High signal-to-noise ratio over a large analog input frequency range (7.8 effective bits
at 4.43 MHz full-scale input at fclk = 40 MHz)
I No missing codes guaranteed
I In-Range (IR) CMOS output
I TTL and CMOS levels compatible digital inputs
I 3 V to 5 V CMOS digital outputs
I Low-level AC clock input signal allowed
I External reference voltage regulator
I Power dissipation only 175 mW (typical)
I Low analog input capacitance, no buffer amplifier required
I No sample-and-hold circuit required
3. Applications
I Video data digitizing
I Radar
I Transient signal analysis
I Σ∆ modulators
I Medical imaging
I Barcode scanner
I Global Positioning System (GPS) receiver


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ADC0804S030/040/050
www.DataSheet4U.com
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
I Cellular base stations
4. Quick reference data
Table 1. Quick reference data
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C;
typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Vi(a)(p-p) = 2.0 V; CL = 15 pF and
Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max Unit
VCCA
VCCD
VCCO
ICCA
ICCD
ICCO
analog supply voltage
digital supply voltage
output supply voltage
analog supply current
digital supply current
output supply current
fclk = 40 MHz;
ramp input
4.75 5.0
4.75 5.0
3.0 3.3
- 18
- 16
-1
5.25 V
5.25 V
5.25 V
24 mA
21 mA
2 mA
INL integral non-linearity fclk = 40 MHz
ramp input
- ±0.2 ±0.5 LSB
DNL
differential non-linearity fclk = 40 MHz
ramp input
- ±0.12 ±0.22 LSB
fclk(max)
maximum clock
frequency
ADC0804S030TS
ADC0804S040TS
30 - - MHz
40 - - MHz
ADC0804S050TS
50 - - MHz
Ptot total power dissipation fclk = 40 MHz;
ramp input
- 175 247 mW
5. Ordering information
Table 2. Ordering information
Type number
Package
Name
Description
ADC0804S030TS SSOP28
ADC0804S040TS SSOP28
ADC0804S050TS SSOP28
plastic shrink small outline package; 28 leads;
body width 5.3 mm
plastic shrink small outline package; 28 leads;
body width 5.3 mm
plastic shrink small outline package; 28 leads;
body width 5.3 mm
Version
Sampling
frequency
(MHz)
SOT341-1 30
SOT341-1 40
SOT341-1 50
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
2 of 19


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6. Block diagram
ADC0804S030/040/050
www.DataSheet4U.com
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
VCCA
3
RT 9
CLK
1
CLOCK DRIVER
VCCD2
11
OE
10
2
TC
analog VI 8
voltage input
RM 7
Rlad
ANALOG - TO - DIGITAL
CONVERTER
LATCHES
CMOS
OUTPUTS
25 D7
24 D6
23 D5
22 D4
21 D3
20 D2
19 D1
18 D0
MSB
data outputs
LSB
RB 6
ADC0804S030
4
AGND
analog ground
Fig 1. Block diagram
12
DGND2
digital ground
13 VCCO
IN-RANGE LATCH
26
CMOS OUTPUT
14
OGND
27
DGND1
28
IR
output
VCCD1
output ground digital ground
014aaa550
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
3 of 19


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7. Pinning information
7.1 Pinning
ADC0804S030/040/050
www.DataSheet4U.com
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
CLK 1
TC 2
VCCA 3
AGND 4
n.c. 5
RB 6
RM 7
VI 8
RT 9
OE 10
VCCD2 11
DGND2 12
VCCO 13
OGND 14
Fig 2. Pin configuration
ADC0804S
030TS
28 VCCD1
27 DGND1
26 IR
25 D7
24 D6
23 D5
22 D4
21 D3
20 D2
19 D1
18 D0
17 n.c.
16 n.c.
15 n.c.
014aaa551
7.2 Pin description
Table 3.
Symbol
CLK
TC
VCCA
AGND
n.c.
RB
RM
VI
RT
OE
VCCD2
DGND2
VCCO
OGND
n.c.
n.c.
n.c.
D0
D1
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Description
clock input
two’s complement input (active LOW)
analog supply voltage (5 V)
analog ground
not connected
reference voltage BOTTOM input
reference voltage MIDDLE
analog input voltage
reference voltage TOP input
output enable input (CMOS level input, active LOW)
digital supply voltage 2 (5 V)
digital ground 2
supply voltage for output stages (3 V to 5 V)
output ground
not connected
not connected
not connected
data output; bit 0 (Least Significant Bit (LSB))
data output; bit 1
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
4 of 19


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ADC0804S030/040/050
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Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Table 3.
Symbol
D2
D3
D4
D5
D6
D7
IR
DGND1
VCCD1
Pin description …continued
Pin Description
20 data output; bit 2
21 data output; bit 3
22 data output; bit 4
23 data output; bit 5
24 data output; bit 6
25 data output; bit 7 (Most Significant Bit (MSB))
26 in-range data output
27 digital ground 1
28 digital supply voltage 1 (5 V)
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
VCCA
VCCD
VCCO
VCC
VI
Vi(clk)(p-p)
analog supply voltage
digital supply voltage
output supply voltage
supply voltage difference
input voltage
VCCA VCCD
VCCD VCCO
VCCA VCCO
referenced to AGND
peak-to-peak clock input referenced to DGND
voltage
[1] 0.3
[1] 0.3
[1] 0.3
1.0
1.0
1.0
0.3
-
IO
Tstg
Tamb
Tj
output current
storage temperature
ambient temperature
junction temperature
-
55
40
-
Max
+7.0
+7.0
+7.0
+1.0
+4.0
+4.0
+7.0
VCCD
10
+150
+85
150
Unit
V
V
V
V
V
V
V
V
mA
°C
°C
°C
[1] The supply voltages VCCA, VCCD and VCCO may have any value between 0.3 V and +7.0 V provided that
the supply voltage differences VCC are respected.
9. Thermal characteristics
Table 5.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
thermal resistance from junction
to ambient
Conditions
in free air
Typ Unit
110 K/W
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
5 of 19


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ADC0804S030/040/050
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Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
10. Characteristics
Table 6. Characteristics
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V, Vi(a)(p-p) = 2.0 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Supplies
VCCA
VCCD
VCCO
VCC
ICCA
ICCD
ICCO
Ptot
Inputs
analog supply voltage
digital supply voltage
output supply voltage
supply voltage
difference
analog supply current
digital supply current
output supply current
total power dissipation
VCCA VCCD
VCCA VCCO
VCCD VCCO
fclk = 40 MHz; ramp input
fclk = 40 MHz; ramp input
4.75
4.75
3.0
0.20
0.20
0.20
-
-
-
-
5.0 5.25 V
5.0 5.25 V
3.3 5.25 V
-
+0.20
V
-
+2.25
V
-
+2.25
V
18 24
mA
16 21
mA
12
mA
175 247
mW
Clock input CLK (referenced to DGND)[1]
VIL LOW-level input voltage
VIH HIGH-level input
voltage
0 - 0.8 V
2
-
VCCD
V
IIL LOW-level input current Vclk = 0.8 V
IIH HIGH-level input current Vclk = 2 V
Zi
input impedance
fclk = 40 MHz
Ci input capacitance
OE and TC (referenced to DGND); see Table 8
1 - +1 µA
- 2 10 µA
-
2-
k
-
2-
pF
VIL LOW-level input voltage
VIH HIGH-level input
voltage
0 - 0.8 V
2
-
VCCD
V
IIL LOW-level input current VIL = 0.8 V
IIH HIGH-level input current VIH = 2.0 V
VI (analog input voltage referenced to AGND)
1
--
µA
-
-1
µA
IIL LOW-level input current VI = VRB = 1.3 V
IIH HIGH-level input current VI = VRT = 3.67 V
Zi
input impedance
fi = 4.43 MHz
Ci input capacitance
Reference voltages for the resistor ladder; see Table 7
-
0-
µA
-
35 -
µA
-
8-
k
-
5-
pF
VRB voltage on pin RB
VRT voltage on pin RT
1.2 1.3 2.45 V
3.2
3.67
VCCA 0.8 V
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
6 of 19


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ADC0804S030/040/050
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Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Table 6. Characteristics
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V, Vi(a)(p-p) = 2.0 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Vref(dif)
differential reference
voltage
VRT VRB
2.0
2.37 3.0
V
Iref
Rlad
TCRlad
reference current
ladder resistance
ladder resistor
temperature coefficient
VRT VRB = 2.37 V
-
-
-
9.7 -
245 -
456 -
mA
m/K
Voffset
Vi(a)(p-p)
offset voltage
peak-to-peak analog
input voltage
BOTTOM;
VRT VRB = 2.37 V
TOP; VRT VRB = 2.37 V
[2] -
[2] -
[3] 1.7
175 -
175 -
2.02 2.55
mV
mV
V
Digital outputs D7 to D0 and IR (referenced to OGND)
VOL
LOW-level output
IOL = 1 mA
voltage
0 - 0.5 V
VOH
HIGH-level output
IOH = 1 mA
voltage
VCCO 0.5 -
VCCO
V
Io
output current
in 3-state mode;
0.5 V < VO < VCCO
Switching characteristics; Clock input CLK; see Figure 4[1]
20 - +20 µA
fclk(max)
maximum clock
frequency
ADC0804S030TS
ADC0804S040TS
30
--
MHz
40
--
MHz
ADC0804S050TS
50
--
MHz
tw(clk)H
HIGH clock pulse width full effective bandwidth
tw(clk)L
LOW clock pulse width full effective bandwidth
Analog signal processing
8.5
5.5
--
--
ns
ns
Linearity
INL
DNL
Eoffset
integral non-linearity
differential non-linearity
offset error
EG gain error
Bandwidth (fclk = 40 MHz)
B bandwidth
fclk = 40 MHz; ramp input
fclk = 40 MHz; ramp input
middle code; VRB = 1.3 V;
VRT = 3.67 V
from device to device;
VRB = 1.3 V; VRT = 3.67 V
full-scale sine wave
-
-
-
[4] -
[5] -
±0.2
±0.12
±0.25
±0.1
±0.5
±0.22
-
-
LSB
LSB
LSB
%
15 -
MHz
75 % full-scale sine wave
-
20 -
MHz
ts(LH)
LOW to HIGH settling
time
small signal at mid-scale;
VI = ±10 LSB at code 512
full-scale square wave; see
Figure 6
-
[6] -
350 -
1.5 3.0
MHz
ns
ts(HL)
HIGH to LOW settling
time
-
1.5 3.0
ns
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
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ADC0804S030/040/050
www.DataSheet4U.com
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Table 6. Characteristics
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V, Vi(a)(p-p) = 2.0 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Harmonics (fclk = 40 MHz); see Figure 7 and 8
α1H
first harmonic level
fi = 4.43 MHz
α2H second harmonic level fi = 4.43 MHz
α3H
third harmonic level
fi = 4.43 MHz
THD
total harmonic distortion fi = 4.43 MHz
Signal-to-noise ratio; see Figure 7 and 8[7]
-
-0
dB
-
75 65
dB
-
72 65
dB
-
65 -
dB
S/N signal-to-noise ratio
Effective number of bits[7]
full scale;
without harmonics;
fclk = 40 MHz; fi = 4.43 MHz
46
49 -
dB
ENOB
effective number of bits
Two-tone intermodulation[8]
ADC0804S030TS (fclk = 30 MHz)
fi = 4.43 MHz
-
fi = 7.5 MHz
-
ADC0804S040TS (fclk = 40 MHz)
fi = 4.43 MHz
-
fi = 7.5 MHz
-
fi = 10 MHz
-
fi = 15 MHz
-
ADC0804S050TS (fclk = 50 MHz)
fi = 4.43 MHz
-
fi = 7.5 MHz
-
fi = 10 MHz
-
fi = 15 MHz
-
7.8 -
7.8 -
7.8 -
7.8 -
7.8 -
7.4 -
7.8 -
7.8 -
7.8 -
7.3 -
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
αIM
intermodulation
fclk = 40 MHz
suppression
-
69 -
dB
Bit error rate
BER
bit error rate
fclk = 40 MHz;
fi = 4.43 MHz; VI = ±16 LSB
at code 512
-
1013
-
times/
samples
Differential gain[9]
Gdif
differential gain
fclk = 40 MHz;
PAL modulated ramp
-
0.8 -
%
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
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ADC0804S030/040/050
www.DataSheet4U.com
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Table 6. Characteristics
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V, Vi(a)(p-p) = 2.0 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Differential phase[9]
ϕdif
differential phase
fclk = 40 MHz;
-
PAL modulated ramp
0.4 -
deg
Timing (fclk = 40 MHz; Ci = 15 pF); see Figure 4[10]
td(s) sampling delay time
th(o) output hold time
td(o)
output delay time
VCCO = 4.75 V
VCCO = 3.15 V
CL load capacitance
3-state output delay times; see Figure 5
-
3-
ns
4
--
ns
-
10 13
ns
-
12 15
ns
- - 15 pF
tdZH float to active HIGH
delay time
-
5.5 8.5
ns
tdZL float to active LOW
delay time
-
12 15
ns
tdHZ active HIGH to float
delay time
-
19 24
ns
tdLZ active LOW to float
delay time
-
12 15
ns
[1] In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less
than 0.5 ns.
[2] Analog input voltages producing code 0 up to and including code 255:
a) Voffset BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB
(VRB) at Tamb = 25 °C.
b) Voffset TOP is the difference between the reference voltage on pin RT (VRT) and the analog input which produces data outputs equal
to code 255 at Tamb = 25 °C.
[3] To ensure the optimum linearity performance of such a converter architecture the lower and upper extremities of the converter reference
resistor ladder are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3.
a) The current flowing into the resistor ladder is I = -------V-----R---T---------V----R---B--------- and the full-scale input range at the converter, to cover code 0
ROB + RL + ROT
to 255 is
VI
=
RL × IL
=
------------------R---L-------------------
ROB + RL + ROT
×
(V RT
+
V
RB)
=
0.852 × (V RT V RB)
b) Since RL, ROB and ROT have similar behavior with respect to process and temperature variation, the ratio -R---O----B-----+----R-R---LL----+-----R----O----T--
will be kept reasonably constant from device to device. Consequently, the variation of the output codes at a given input voltage
depends mainly on the difference VRT VRB and its variation with temperature and supply voltage. When several ADCs are
connected in parallel and fed with the same reference source, the matching between each of them is optimized.
[4]
EG
=
(---V----1---0--2--3---------V----0---)--------V----i--(--p-------p---)
Vi(p p)
×
100
[5] The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater
than 0.5 LSB, neither any significant attenuation are observed in the reconstructed signal.
[6] The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square
wave signal) in order to sample the signal and obtain correct output data.
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
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ADC0804S030/040/050
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Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
[7] Effective bits are obtained via a Fast Fourier transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental
period. The calculation takes into account all harmonics and noise up to half the clock frequency (Nyquist frequency). Conversion to
SIgnal-to-Noise-And-Distortion (SINAD) ratio: SINAD = ENOB × 6.02 + 1.76 dB.
[8] Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have
the same amplitude and the total amplitude of both signals provides full-scale to the converter.
[9] Measurement carried out using video analyzer VM700A, where the video analog signal is reconstructed through a digital-to-analog
converter.
[10] Output data acquisition: the output data is available after the maximum delay time of td(0). For 50 MHz version NXP recommend the
lowest possible output load.
RT
ROT
code 255
RL
RL
RM IL
Rlad
RL
RL
code 0
ROB
RB
014aaa555
Fig 3. Explanation of Table 6 Table note 3
11. Additional information relating to Table 6
Table 7.
Code
Output coding and input voltage (typical values; referenced to AGND, VRB = 1.3 V,
VRT = 3.67 V)
Vi(a)(p-p) IR
(V)
Binary outputs D7 to D0 Two’s complement
outputs D7 to D0
Underflow < 1.475 0
0000 0000
10 0000 00
0
1.475
1
0000 0000
10 0000 00
1 - 1 0000 0001
10 0000 01
- ↓↓
254 -
1 1111 1110
01 1111 10
255
3.495
1
1111 1111
01 1111 11
Overflow
> 3.495 0
1111 1111
01 1111 11
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
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ADC0804S030/040/050
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Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Table 8.
TC
X
0
1
Mode selection
OE D7 to D0
1 high impedance
0 active; two’s complement
0 active; binary
IR
high impedance
active
active
CLK
sample N
sample N + 1
tw(clk)H
tw(clk)L
sample N + 2
sample N
sample N + 1
sample N + 2
VCCO
50 %
0V
VI
DATA
D0 to D7
td(s)
DATA
N2
Fig 4. Timing diagram
DATA
N1
td(o)
th(o)
DATA
N
DATA
N+1
VCCO
50 %
0V
014aaa556
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
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ADC0804S030/040/050
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Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
VCCD
OE
50 %
output
data
output
data
LOW
HIGH
tdLZ
tdZL
HIGH
10 %
50 %
tdHZ
tdZH
90 %
LOW
50 %
ADC0804S030
OE
3.3 k
15 pF
VCCD
S1
TEST
tdLZ
tdZL
tdHZ
tdZH
S1
VCCD
VCCD
DGND
DGND
014aaa552
frequency on pin OE = 100 kHz
Fig 5. Timing diagram and test conditions of 3-state output delay time
code 255
VI
code 0
ts(LH)
50 %
2 ns
ts(HL)
50 %
2 ns
CLK
50 %
0.5 ns
Fig 6. Analog input settling time diagram
50 %
0.5 ns
014aaa400
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
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Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
+20
amplitude
(dB)
20
014aaa328
60
100
140
0
5.00
10.0
15.0
Fig 7.
Effective bits: 7.84; THD = 71.8 dB.
Harmonic levels (dB): 2nd = 83.19; 3rd = 78.09; 4th = 78.72; 5th = 78.33; 6th = 77.55.
Typical fast Fourier transform (fclk = 40 MHz; fi = 4.43 MHz)
f (MHz)
20.0
+20
amplitude
(dB)
20
014aaa329
60
100
140
0
5.0
10.0
15.0
20.0
Fig 8.
Effective bits: 7.79; THD = 62.96 dB.
Harmonic levels (dB): 2nd = 71.38; 3rd = 71.54; 4th = 74.14; 5th = 65.15; 6th = 77.16.
Typical fast Fourier transform (fclk = 50 MHz; fi = 10 MHz)
f (MHz)
25.0
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Product data sheet
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Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
VCCO
VCCA
D7 to D0
IR
VI
OGND
014aaa557
Fig 9. CMOS data and in-range outputs
VCCO
AGND
Fig 10. Analog inputs
VCCA
RT
OE
TC
OGND
Fig 11. OE and TC input
RM
014aaa553
RB
AGND
Fig 12. RB, RM and RT
014aaa526
RL
RL
RL
RL
014aaa331
VCCD
CLK
DGND
1.5 V
ADC0804S030_040_050_2
Product data sheet
Fig 13. CLK input
Rev. 02 — 14 August 2008
014aaa399
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12. Application information
ADC0804S030/040/050
www.DataSheet4U.com
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
CLK
TC
VCCA
(3) 100 nF AGND
100 nF
100 nF
AGND
AGND
n.c.
RB(1)
RM(1)
VI
RT(1)
100 nF
AGND (3)
(3)
OE
VCCD2
100 nF DGND2
100 nF
VCCO
OGND
1 28
2 27
3 26
4 25
5 24
6 23
7 22
ADC0804S030
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCCD1
DGND1
IR
D7
D6
D5
D4
D3
D2
D1
D0
n.c.
n.c.
n.c.(2)
(3)
100 nF
014aaa554
The analog and digital supplies should be separated and well decoupled
A user manual is available that describes the demonstration board that uses the version ADC0804S030/040/050/ family with an
application environment.
(1) RB, RM and RT are decoupled to AGND.
(2) Pin 15 may be connected to DGND in order to prevent noise influence.
(3) Decoupling capacitor for supplies; must be placed close to the device.
Fig 14. Application diagram
12.1 Alternative parts
The following alternative parts are also available:
Table 9. Alternative parts
Type number
Description
ADC1004S030
Single 10 bits ADC
ADC1004S040
Single 10 bits ADC
ADC1004S050
Single 10 bits ADC
ADC1003S030
Single 10 bits ADC
[1]
[1]
[1]
[1]
ADC1003S040
Single 10 bits ADC
[1]
ADC1003S050
Single 10 bits ADC
[1]
ADC1005S060
[1] Pin to pin compatible
Single 10 bits ADC
[1]
Sampling frequency
30 MHz
40 MHz
50 MHz
30 MHz, with internal reference
regulator
40 MHz, with internal reference
regulator
50 MHz, with internal reference
regulator
60 MHz
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
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Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
13. Package outline
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
y
Z
28
D
pin 1 index
1
e
c
15
EA
X
HE v M A
14
wM
bp
A2
A1
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c D(1) E(1) e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
10.4
10.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2 0.13 0.1
1.1
0.7
8o
0o
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
SOT341-1
IEC
REFERENCES
JEDEC
JEITA
MO-150
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 15. SOT341-1 (SSOP28)
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
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Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
14. Revision history
Table 10. Revision history
Document ID
Release date Data sheet status
Change
notice
Supersedes
ADC0804S030_040_050_2 20080814
Product data sheet
-
ADC0804S030_040_050_1
Modifications:
Paragraph added to Section 1.
Corrections to descriptions of rows RB and RM in Table 3.
Corrections to Table 6.
Corrections to Figure 9, 10 and 12.
ADC0804S030_040_050_1 20080616
Product data sheet
-
-
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
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Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Objective [short] data sheet Development
Preliminary [short] data sheet Qualification
Product [short] data sheet
Production
Definition
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
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Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5
10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6
11 Additional information relating to Table 6 . . . 10
12 Application information. . . . . . . . . . . . . . . . . . 15
12.1 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 15
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16 Contact information. . . . . . . . . . . . . . . . . . . . . 18
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 August 2008
Document identifier: ADC0804S030_040_050_2




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