74HC148 Datasheet PDF
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October 1987
Revised February 1999
MM74HC148
8-3 Line Priority Encoder
General Description
The MM74HC148 priority encoder utilizes advanced sili-
con-gate CMOS technology. It has the high noise immunity
and low power consumption typical of CMOS circuits, as
well as the speeds and output drive similar to LB-TTL.
This priority encoder accepts 8 input request lines 0–7 and
outputs 3 lines A0–A2. The priority encoding ensures that
only the highest order data line is encoded. Cascading cir-
cuitry (enable input EI and enable output EO) has been
provided to allow octal expansion without the need for
external circuitry. All data inputs and outputs are active at
the low logic level.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to VCC and ground.
Features
s Typical propagation delay: 13 ns
s Wide supply voltage range: 2V–6V
Ordering Code:
Order Number Package Number
Package Description
MM74HC148M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC148MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC148N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC and TSSOP
Inputs
Outputs
EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO
HXXXXXXXX H H H H H
L HHHHHHHH H H H H L
L XXXXXXXL L L L L H
L XXXXXXLH L L H L H
L XXXXX LHH L H L L H
L XXXX LHHH L H H L H
L XXX LHHHH H L L L H
L XX LHHHHH H L H L H
L X LHHHHHH H H L L H
L LHHHHHHH H H H L H
H = HIGH
L = LOW
X = Irrelevant
© 1999 Fairchild Semiconductor Corporation DS009390.prf
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Schematic Diagram
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Logic Diagram
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Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC)
0.5 to +7.0V
DC Input Voltage (VIN)
1.5 to VCC +1.5V
DC Output Voltage (VOUT)
0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)
±20 mA
DC Output Current, per pin (IOUT)
±25 mA
DC VCC or GND Current, per pin (ICC)
±50 mA
Storage Temperature Range (TSTG)
65°C to +150°C
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (TL)
(Soldering 10 seconds)
260°C
Recommended Operation
Conditions
Min Max Units
Supply Voltage (VCC)
DC Input or Output Voltage
26V
(VIN, VOUT)
Operating Temperature Range (TA)
0 VCC
40 +85
V
°C
Input Rise or Fall Times
(tr, tf) VCC = 2.0V
1000 ns
VCC = 4.5V
500 ns
VCC = 6.0V
400 ns
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating—plastic “N” package: 12
mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TA = 25°C
TA = −40 to 85°C TA = −55 to 125°C
Units
Typ Guaranteed Limits
VIH Minimum HIGH Level
Input Voltage
2.0V
4.5V
1.5
3.15
1.5
3.15
1.5
3.15
V
V
6.0V
4.2 4.2
4.2 V
VIL Maximum LOW Level
Input Voltage
2.0V
4.5V
0.5
1.35
0.5
1.35
0.5
1.35
V
V
6.0V
1.8 1.8
1.8 V
VOH Minimum HIGH Level
Output Voltage
VIN = VIH or VIL
|IOUT| 20 µA
2.0V
4.5V
2.0
4.5
1.9
4.4
1.9
4.4
1.9 V
4.4 V
6.0V
6.0
5.9
5.9
5.9 V
VOL Maximum LOW Level
Output Voltage
VIN = VIH or VIL
|IOUT| 4.0 mA
|IOUT| 5.2 mA
VIN = VIH or VIL
|IOUT| 20 µA
4.5V
6.0V
2.0V
4.5V
4.7
5.2
0
0
3.96
5.48
0.1
0.1
3.84
5.34
0.1
0.1
3.7 V
5.2 V
0.1 V
0.1 V
6.0V
0
0.1
0.1
0.1 V
IIN Maximum Input
Current
VIN = VIH or VIL
|IOUT| 4.0 mA
|IOUT| 5.2 mA
VIN = VCC or GND
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
±0.1
0.33
0.33
±1.0
0.4
0.4
±1.0
V
V
µA
ICC Maximum Quiescent
VIN = VCC or GND
6.0V
8.0 80
160 µA
Supply Current
IOUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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AC Electrical Characteristics
Symbol
tPHL, tPLH
Parameter
Maximum Propagation Delay,
Any Input to Any Output
Conditions
Typ
Guaranteed
Limits
Units
14 ns
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC TA = 25°C
Typ
TA = −40°C to +85°C TA = −55°C to +125°C Units
Guaranteed Limits
tPHL, tPLH Inputs 0–7
to Outputs
2.0V
4.5V
14
140
28
175
35
210 ns
42 ns
A0, A1, A2
6.0V
24 30
36 ns
tPHL, tPLH Inputs 0–7
to
2.0V
4.5V
15
140
28
175
35
210 ns
42 ns
Output EO
6.0V
24 30
36 ns
tPHL, tPLH Inputs 0–7
to
2.0V
4.5V
17
160
32
200
40
240 ns
48 ns
Output GS
6.0V
27 34
41 ns
tPHL, tPLH Input EI
to Outputs
2.0V
4.5V
17
160
32
200
40
240 ns
48 ns
A0, A1, A2
6.0V
27 34
41 ns
tPHL, tPLH Input EI
to
2.0V
4.5V
12
100
20
125
25
150 ns
30 ns
Output GS
6.0V
17 21
26 ns
tPHL, tPLH Input EI
to
2.0V
4.5V
12
100
20
125
25
150 ns
30 ns
Output EO
6.0V
17 21
26 ns
tf, tr Maximum
Output Rise
2.0V
4.5V
7
75
15
95
19
110 ns
22 ns
and Fall Time
6.0V
13 16
19 ns
Cpd Power Dissipation
Capacitance (Note 5)
52
pF
Cin Maximum Input
Capacitance
5 10
10
10 pF
Note 5: Cpd determines the no load dynamic power consumption, and the no load dynamic current consumption.
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.



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