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J105 / J106 / J107
N-Channel Switch
Description
This device is designed for analog or digital switching
applications where very low on resistance is manda-
tory. Sourced from Process 59.
September 2013
Ordering Informations
Part Number
J105
J106
J107
Marking
J105
J106
J107
Package
TO-92 3L
Packing Method
Bulk
Absolute Maximum Ratings(1)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted.
Symbol
Parameter
Value
Units
VDG
VGS
IGF
TJ, Tstg
Drain-Gate Voltage
Gate-Source Voltage
Forward Gate Current
Operating and Storage Junction Temperature Range
25
-25
10
-55 to +150
V
V
mA
°C
Notes:
1. These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
2. These ratings are based on a maximum junction temperature of 150°C.
3. These are steady-state limits. The factory should be consulted on applications involving pulsed or low duty
cycle operations.
© 1997 Fairchild Semiconductor Corporation
J105 / J106 / J107 Rev. 1.1.1
1
www.fairchildsemi.com


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Thermal Characteristics(4)
Values are at TA = 25°C unless otherwise noted.
Symbol
Parameter
Maximum
Units
PD
Power Dissipation
Derate above 25°C
625 mW
5.0 mW/°C
RθJC Thermal Resistance, Junction to Case
125 °C/W
RθJA Thermal Resistance, Junction to Ambient
357 °C/W
Note:
4. PCB board size FR-4 76 x 114 x 0.6T mm3 (3.0 inch x 4.5 inch x 0.062 inch) with minimum land pattern size.
Electrical Characteristics
Values are at TA = 25°C unless otherwise noted.
Symbol
Parameter
OFF CHARACTERISTICS
V(BR)GSS
Gate-Source Breakdown
Voltage
IGSS
ID(off)
Gate Reverse Current
Gate-Source Cut-Off Voltage
VGS(off) Gate-Source Cut-Off Voltage
ON CHARACTERISTICS
IDSS
Zero-Gate Voltage Drain
Current(5)
RDS(on) Drain-Source On Resistance
Test Conditions
IG = -10 μA, VDS = 0
VGS = -15 V, VDS = 0
VGS = -15 V, VDS = 0, TA = 100°C
VDS = -5.0 V, VGS = -10 V
J105
VDS = 5.0 V, ID = 1.0 mA
J106
J107
VDS = 15 V, IGS = 0
VDS 0.1 V, VGS = 0
J105
J106
J107
J105
J106
J107
SMALL SIGNAL CHARACTERISTICS
Cdg(on)
Csg(on)
Cdg(off)
Csg(off)
Drain-Gate On Capacitance
Source-Gate On Capacitance
Drain-Gate Off Capacitance
Source-Gate Off Capacitance
VDS = 0, VGS = 10 V, f = 1.0 MHz
Note:
5. Pulse test: pulse width 300 μs, duty cycle 2.0%.
Min
-25
-4.5
-2.0
-0.5
500
200
100
Max Units
-3.0
-200
3.0
-10.0
-6.0
-4.5
V
nA
nA
V
mA
3.0
6.0 Ω
8.0
160 pF
35
pF
pF
© 1997 Fairchild Semiconductor Corporation
J105 / J106 / J107 Rev. 1.1.1
2
www.fairchildsemi.com


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Typical Performance Characteristic
350
T = 25 oC
A
300
V = -4.5 V max
GS(off)
250
V =0V
GS
200 V = -1 V
GS
150
100
V = -2 V
GS
50
0
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Drain-Source Volatage, V [V]
DS
Figure 1. Common Drain-Source Characteristics
500
T = 25 oC
A
V = -4.5 V max
GS(off)
400
V =0V
GS
V = -0.1 V
GS
V = -0.2 V
GS
300
200
V = -0.3 V
GS
V = -0.4 V
GS
V = -0.5 V
GS
100
0
012345
Drain-Source Voltage, V [V]
DS
Figure 2. Common Drain-Source Characteristics
Figure 3. Parameter Interactions
Figure 4. Capacitance vs. Voltage
Figure 5. Normalized Drain Resistance vs.
Bias Voltage
Figure 6. On Resistance vs. Drain Current
© 1997 Fairchild Semiconductor Corporation
J105 / J106 / J107 Rev. 1.1.1
3
www.fairchildsemi.com


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Typical Performance Characteristic (Continued)
Figure 7. Output Conductance vs. Drain Current
Figure 9. Noise Voltage vs. Frequency
Figure 8. Transconductance vs. Drain Current
1.00
0.75
TO-92
0.50
0.25
0.00
0
25 50 75 100 125 150 175 200
Temperature [oC]
Figure 10. Power Dissipation vs. Ambient
Temperature
© 1997 Fairchild Semiconductor Corporation
J105 / J106 / J107 Rev. 1.1.1
4
www.fairchildsemi.com


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Physical Dimensions
TO-92
D
Figure 11. 3-LEAD, TO-92, MOLDED, STD STRAIGHT LD (NO EOL CODE)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/ZA/ZA03D.pdf.
© 1997 Fairchild Semiconductor Corporation
J105 / J106 / J107 Rev. 1.1.1
5
www.fairchildsemi.com


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Rev. I66
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