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TDA7478
SINGLE CHIP RDS DEMODULATOR
1 FEATURES
VERY HIGH RDS DEMODULATION QUALITY
WITH IMPROVED DIGITAL SIGNAL
PROCESSING
HIGH PERFORMANCE, 57KHz BANDPASS
FILTER (8th ORDER)
FILTER ADJUSTMENT FREE AND WITHOUT
EXTERNAL COMPONENTS
PURELY DIGITAL RDS DEMODULATION
WITHOUT EXTERNAL COMPONENTS
RDS SIGNAL QUALITY OUTPUT
4.332MHz CRYSTAL OSCILLATOR(8.664MHz
OPTIONAL)
LOW NOISE CMOS TECHNOLOGY
LOW RADIATION
2 DESCRIPTION
The TDA7478 recovers the additional inaudible RDS
information which is transmitted by FM radio broad-
casting stations and operates in accordance with the
Figure 2. Block Diagram
Figure 1. Packages
SO16
Table 1. Order Codes
Part Number
TDA7478D
E-TDA7478AD
TSSOP16
Package
SO16
TSSOP16
EBU (European Broadcasting Union) specifications.
The device is made up of two sections: a cascaded
antialiasing + switched capacitors 8th bandpass filter
for precise RDS band selection and a demodulating
section that performs the extraction od RDS data
stream (RDDA) and clock (RDCL), to be further pro-
cessed by a suitable RDS decoder.
Output for RDS signal quality is also present.
C1 27pF 4.332MHz C2 47pF
MPX
270pF
4
8
FILOUT
VS
100nF
10µF
12
VREF 3
2nd ORDER
ANTIALIASING
FILTER
8th ORDER
SC-BANDPASS
FILTER
-
+
T57
15
OSCIN
13
OSCOUT
14
OSCILLATOR &
DIVIDER
57KHz PLL
1187.5Hz
PLL
QUAL DET.
5
OSEL
9
FSEL
16
RDCL
7
N.U.
1
QUAL
POLARITY
BIPHASE DEC.
INTEGRAL
BIPHASE DEC.
0
MUX
1
DIFF. DECODER
2
RDDA
TEST LOGIC
10
TM
November 2004
6
GND
11
EXTRES
D03AU1490
Rev. 2
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TDA7478
Table 2. Pin Description
No pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
QUAL
RDDA
VREF
MPX
OSEL
GND
N.U.
FILOUT
FSEL
TM
EXTRES
VS
OSCIN
OSCOUT
T57
RDCL
Description
Output for signal quality indication (High = good)
RDS data output
Reference voltage
RDS input signal
Oscillator selector pin:
- open, closed to VS = quartz oscillator
- closed to GND=external driven
Ground
Not Used (to be left open)
Filter output
Frequency selector pin:
- open = 4.332MHz
- closed to VS = 8.664MHz
Test mode pin: - open = normal operation - closed to VS = testmode
Reset pin: - open=run mode - closed to VS = reset condition
Supply voltage
Oscillator input
Oscillator output
Testing output pin: 57kHz clock output
RDS clock output 1187.5Hz
Figure 3. Pin Connection (Top view)
QUAL
RDDA
VREF
MPX
OSEL
GND
N.U.
FILOUT
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
D97AU752A
RDCL
T57
OSCOUT
OSCIN
VS
EXTRES
TM
FSEL
Table 3. Thermal Data
Symbol
Description
Rth j-case Thermal Resistance Junction-case Max.
Value
200
Unit
°C/W
2/8


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Table 4. Absolute Maximum Ratings
Symbol
VS
Top
Tstg
Parameter
Supply Voltage
Operating Temperature Range
Storage Temperature
TDA7478
Value
-0.3 to 7
-40 to 85
-55 to 150
Unit
V
°C
°C
Table 5. Electrical Characteristcs
(Tamb = 25°C, VS = 5V, unless otherwise specified)
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
VS Supply voltage
4.5 5 5.5 V
IS Supply current
7.5 12.0 mA
FILTER
fC Center frequency
56.6 57 57.4 kHz
BW 3dB Bandwidth
2.5 3 3.5 kHz
G Gain
f = 57kHz
17 20 23 dB
A Attenuation
f ± 4kHz
22 dB
f = 38kHz
60 dB
f = 67kHz
45 dB
RI Input impedance of MPX
120 K
RL Load impedance on FILOUT
1 M
S/N Signal to noise ratio
VIN = 3mVRMS
30 40
dB
VIN MPX input signal
f = 19kHz; T3 40dB(1)
f = 57kHz (RDS)
1000 mVRMS
50 mVRMS
SRDS RDS Detection Sensitivity
1 mVrms
SARI ARI Detection Sensitivity
3 mVrms
VREF Reference
VS/2
V
DEMODULATOR
Input pins (EXTRES, FSEL, TM)
Input pin (OSEL)
all with internal pull down resistor
with internal pull up resistor
IPD Input Current
VIN = 5V (pull-down input)
15
30 µA
IPU Input Current
VIN = 0V (pull-up input) -25 -10 µA
VIH Input voltage high
0.7 · VS 0.8 · VS
V
VIL Input voltage low
0.2 · VS 0.3 · VS V
Output pins (RDCL, RDDA, QUAL, T57)
VOH Ouput voltage high
IL = 0.5mA
4 4.6
V
VOL Output voltage low
IL = 0.5mA
0.4 1
V
OSCILLATOR
VCLL Input level OSCIN pin
OSEL = open circuit
1V
VCLH Input level OSCIN pin
OSEL = open circuit
4
V
Amplitude OSCOUT
OSEL = open circuit
4.5 V
VPP Amplitude OSCIN
(for external drive)
OSEL = GND, f = 4.332MHz
OSEL = GND, f = 8.664MHz
100 mVpp
120 mVpp
(1) The 3rd harmonic (57kHz) must be less than -40dB with respect to the input signal plus gain.
3/8


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TDA7478
Figure 4. RDS timing diagram
CLOCK
LINE
DATA
LINE
3 OUTPUT TIMING
The RDS (1187.5Hz) output clock on RDCL line is synchronized to the incoming data. According to the internal
PLL lock condition data change can result on the falling or on the rising clock edge. (see Fig. 1)Whichever clock
edge is used by the decoder (rising or falling edge) the data will remain valid for 416.7 µs after the clock transi-
tion.
4 OSCILLATOR CONTROLS (FSEL, OSEL)
Two different crystal frequencies can be used. The adaption of the internal clock divider to the external crystal
is achieved via the input pin FSEL. See the following table for reference:
Table 6.
Crystal
4.332MHz
8.664MHz
connected to GND or open
connected to Vs
FSEL (pin configuration)
A special mode is introduced to reduce EMI. With pin OSEL connected to GND the internal oscillator is switched
off and an external sinusoidal frequency could be applied on OSCIN. The peak to peak voltage of this signal
can be reduced down to 60mV.
In this mode the frequency selection via FSEL is still active.
Suggested values of C1 and C2 are shown in the following table:
Table 7.
Crystal
4.332MHz
8.664MHz
C1
27pF
27pF
C2
47pF
-
4/8


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TDA7478
Figure 5. SO16 Mechanical Data & Package Dimensions
DIM.
MIN.
mm
TYP.
MAX. MIN.
inch
TYP. MAX.
A 2.35
2.65 0.093
0.104
A1 0.10
0.30 0.004
0.012
B 0.33
0.51 0.013
0.200
C 0.23
0.32 0.009
0.013
D (1) 10.10
10.50 0.398
0.413
E 7.40
7.60 0.291
0.299
e 1.27
0.050
H 10.0
10.65 0.394
0.419
h 0.25
0.75 0.010
0.030
L 0.40
1.27 0.016
0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
OUTLINE AND
MECHANICAL DATA
SO16 (Wide)
0016021 C
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TDA7478
Figure 6. TSSOP16 Mechanical Data & Package Dimensions
DIM.
MIN.
mm
TYP.
MAX. MIN.
inch
TYP. MAX.
A
1.200
0.047
A1 0.050
0.150 0.002
0.006
A2 0.800 1.000 1.050 0.031 0.039 0.041
b 0.190
0.300 0.007
0.012
c 0.090
0.200 0.005
0.009
D (1) 4.900 5.000 5.100 0.114 0.118 0.122
E 6.200 6.400 6.600 0.244 0.252 0.260
E1 (1) 4.300 4.400 4.500 0.170 0.173 0.177
e 0.650
0.026
L 0.450 0.600 0.750 0.018 0.024 0.030
L1 1.000
0.039
k 0˚ (min.) 8˚ (max.)
aaa
0.100
0.004
Note: 1. D and E1 does not include mold flash or protrusions.
Mold flash or potrusions shall not exceed 0.15mm
(.006inch) per side.
OUTLINE AND
MECHANICAL DATA
TSSOP16
(Body 4.4mm)
0080338 (Jedec MO-153-AB)
6/8


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Table 8. Revision History
Date
Revision
July 2004
1
November 2004
2
TDA7478
Description of Changes
First Issue
Add in the table 5 “RDS and ARI Detection Sensitivity” parameters.
7/8


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TDA7478
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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