National Semiconductor Electronic Components Datasheet


ADC0804

8-Bit uP Compatible A/D Converters


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November 1999
ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
8-Bit µP Compatible A/D Converters
General Description
The ADC0801, ADC0802, ADC0803, ADC0804 and
ADC0805 are CMOS 8-bit successive approximation A/D
converters that use a differential potentiometric
ladder — similar to the 256R products. These converters are
designed to allow operation with the NSC800 and INS8080A
derivative control bus with TRI-STATE® output latches di-
rectly driving the data bus. These A/Ds appear like memory
locations or I/O ports to the microprocessor and no interfac-
ing logic is needed.
Differential analog voltage inputs allow increasing the
common-mode rejection and offsetting the analog zero input
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Features
n Compatible with 8080 µP derivatives — no interfacing
logic needed - access time - 135 ns
n Easy interface to all microprocessors, or operates “stand
alone”
n Differential analog voltage inputs
n Logic inputs and outputs meet both MOS and TTL
voltage level specifications
n Works with 2.5V (LM336) voltage reference
n On-chip clock generator
n 0V to 5V analog input voltage range with single 5V
supply
n No zero adjust required
n 0.3" standard width 20-pin DIP package
n 20-pin molded chip carrier or small outline package
n Operates ratiometrically or with 5 VDC, 2.5 VDC, or
analog span adjusted voltage reference
Key Specifications
n Resolution
n Total error
n Conversion time
8 bits
±14 LSB, ±12 LSB and ±1 LSB
100 µs
Connection Diagram
ADC080X
Dual-In-Line and Small Outline (SO) Packages
Ordering Information
TEMP RANGE
±14 Bit Adjusted
ERROR
±12 Bit Unadjusted
±12 Bit Adjusted
±1Bit Unadjusted
PACKAGE OUTLINE
DS005671-30
See Ordering Information
0˚C TO 70˚C
ADC0802LCWM
ADC0804LCWM
M20B — Small
Outline
0˚C TO 70˚C
−40˚C TO +85˚C
ADC0801LCN
ADC0802LCN
ADC0803LCN
ADC0804LCN
ADC0805LCN/ADC0804LCJ
N20A — Molded DIP
TRI-STATE® is a registered trademark of National Semiconductor Corp.
Z-80® is a registered trademark of Zilog Corp.
© 1999 National Semiconductor Corporation DS005671
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Typical Applications
8080 Interface
DS005671-1
DS005671-31
Part
Number
ADC0801
ADC0802
ADC0803
ADC0804
ADC0805
Error Specification (Includes Full-Scale,
Zero Error, and Non-Linearity)
Full-
Scale
VREF/2=2.500 VDC
(No Adjustments)
VREF/2=No Connection
(No Adjustments)
Adjusted
±14 LSB
±12 LSB
±12 LSB
±1 LSB
±1 LSB
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC) (Note 3)
Voltage
Logic Control Inputs
At Other Input and Outputs
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package
Vapor Phase (60 seconds)
6.5V
−0.3V to +18V
−0.3V to (VCC+0.3V)
260˚C
300˚C
215˚C
Infrared (15 seconds)
Storage Temperature Range
Package Dissipation at TA=25˚C
ESD Susceptibility (Note 10)
220˚C
−65˚C to +150˚C
875 mW
800V
Operating Ratings (Notes 1, 2)
Temperature Range
ADC0804LCJ
ADC0801/02/03/05LCN
ADC0804LCN
ADC0802/04LCWM
Range of VCC
TMINTATMAX
−40˚CTA+85˚C
−40˚CTA+85˚C
0˚CTA+70˚C
0˚CTA+70˚C
4.5 VDC to 6.3 VDC
Electrical Characteristics
The following specifications apply for VCC=5 VDC, TMINTATMAX and fCLK=640 kHz unless otherwise specified.
Parameter
Conditions
Min Typ Max
ADC0801: Total Adjusted Error (Note 8)
With Full-Scale Adj.
±14
(See Section 2.5.2)
ADC0802: Total Unadjusted Error (Note 8)
ADC0803: Total Adjusted Error (Note 8)
VREF/2=2.500 VDC
With Full-Scale Adj.
±12
±12
(See Section 2.5.2)
ADC0804: Total Unadjusted Error (Note 8)
ADC0805: Total Unadjusted Error (Note 8)
VREF/2 Input Resistance (Pin 9)
VREF/2=2.500 VDC
VREF/2-No Connection
ADC0801/02/03/05
ADC0804 (Note 9)
2.5
0.75
8.0
1.1
±1
±1
Analog Input Voltage Range
DC Common-Mode Error
(Note 4) V(+) or V(−)
Over Analog Input Voltage
Gnd–0.05
±1/16
VCC+0.05
±18
Range
Power Supply Sensitivity
VCC=5 VDC ±10% Over
Allowed VIN(+) and VIN(−)
Voltage Range (Note 4)
±1/16
±18
Units
LSB
LSB
LSB
LSB
LSB
k
k
VDC
LSB
LSB
AC Electrical Characteristics
The following specifications apply for VCC=5 VDC and TMINTATMAX unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max
TC Conversion Time
TC Conversion Time
fCLK Clock Frequency
Clock Duty Cycle
fCLK=640 kHz (Note 6)
(Notes 5, 6)
VCC=5V, (Note 5)
103 114
66 73
100 640 1460
40 60
CR Conversion Rate in Free-Running INTR tied to WR with
8770
9708
tW(WR)L
tACC
Mode
Width of WR Input (Start Pulse Width)
Access Time (Delay from Falling
Edge of RD to Output Data Valid)
CS =0 VDC, fCLK=640 kHz
CS =0 VDC (Note 7)
CL=100 pF
100
135 200
t1H, t0H
TRI-STATE Control (Delay
from Rising Edge of RD to
CL=10 pF, RL=10k
(See TRI-STATE Test
125 200
Hi-Z State)
Circuits)
tWI, tRI
Delay from Falling Edge
of WR or RD to Reset of INTR
300 450
CIN Input Capacitance of Logic
Control Inputs
5 7.5
Units
µs
1/fCLK
kHz
%
conv/s
ns
ns
ns
ns
pF
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AC Electrical Characteristics (Continued)
The following specifications apply for VCC=5 VDC and TMINTATMAX unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max
COUT
TRI-STATE Output
Capacitance (Data Buffers)
5 7.5
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
VIN (1)
Logical “1” Input Voltage
(Except Pin 4 CLK IN)
VCC=5.25 VDC
2.0 15
VIN (0)
Logical “0” Input Voltage
(Except Pin 4 CLK IN)
VCC=4.75 VDC
0.8
IIN (1)
Logical “1” Input Current
(All Inputs)
VIN=5 VDC
0.005
1
IIN (0)
Logical “0” Input Current
(All Inputs)
VIN=0 VDC
−1 −0.005
CLOCK IN AND CLOCK R
VT+ CLK IN (Pin 4) Positive Going
Threshold Voltage
2.7 3.1 3.5
VT− CLK IN (Pin 4) Negative
Going Threshold Voltage
1.5 1.8 2.1
VH
VOUT (0)
CLK IN (Pin 4) Hysteresis
(VT+)−(VT−)
Logical “0” CLK R Output
Voltage
VOUT (1)
Logical “1” CLK R Output
Voltage
DATA OUTPUTS AND INTR
IO=360 µA
VCC=4.75 VDC
IO=−360 µA
VCC=4.75 VDC
0.6 1.3 2.0
0.4
2.4
VOUT (0)
Logical “0” Output Voltage
Data Outputs
INTR Output
VOUT (1)
VOUT (1)
IOUT
Logical “1” Output Voltage
Logical “1” Output Voltage
TRI-STATE Disabled Output
Leakage (All Data Buffers)
ISOURCE
ISINK
POWER SUPPLY
IOUT=1.6 mA, VCC=4.75 VDC
0.4
IOUT=1.0 mA, VCC=4.75 VDC
0.4
IO=−360 µA, VCC=4.75 VDC
2.4
IO=−10 µA, VCC=4.75 VDC
4.5
VOUT=0 VDC
−3
VOUT=5 VDC
3
VOUT Short to Gnd, TA=25˚C
4.5
6
VOUT Short to VCC, TA=25˚C
9.0
16
ICC Supply Current (Includes
Ladder Current)
fCLK=640 kHz,
VREF/2=NC, TA=25˚C
and CS =5V
ADC0801/02/03/04LCJ/05
1.1 1.8
ADC0804LCN/LCWM
1.9 2.5
Units
pF
VDC
VDC
µADC
µADC
VDC
VDC
VDC
VDC
VDC
VDC
VDC
VDC
VDC
µADC
µADC
mADC
mADC
mA
mA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.
Note 3: A zener diode exists, internally, from VCC to Gnd and has a typical breakdown voltage of 7 VDC.
Note 4: For VIN(−)VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct
for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high
level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows
50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct.
To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance
and loading.
Note 5: Accuracy is guaranteed at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be ex-
tended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.
Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The
start request is internally latched, see Figure 4 and section 2.0.
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AC Electrical Characteristics (Continued)
Note 7: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold
the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams).
Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and Figure 7.
Note 9: The VREF/2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802, ADC0803, and
ADC0805, and in the ADC0804LCJ, each resistor is typically 16 k. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 k.
Note 10: Human body model, 100 pF discharged through a 1.5 kresistor.
Typical Performance Characteristics
Logic Input Threshold Voltage
vs. Supply Voltage
Delay From Falling Edge of
RD to Output Data Valid
vs. Load Capacitance
CLK IN Schmitt Trip Levels
vs. Supply Voltage
DS005671-38
fCLK vs. Clock Capacitor
Full-Scale Error vs
Conversion Time
DS005671-39
DS005671-40
Effect of Unadjusted Offset Error
vs. VREF/2 Voltage
Output Current vs
Temperature
DS005671-41
DS005671-42
Power Supply Current
vs Temperature (Note 9)
DS005671-43
Linearity Error at Low
VREF/2 Voltages
DS005671-44
DS005671-45
5
DS005671-46
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TRI-STATE Test Circuits and Waveforms
t1H
t1H, CL=10 pF
t0H
DS005671-47
tr=20 ns
DS005671-48
t0H, CL=10 pF
DS005671-49
tr=20 ns
Timing Diagrams (All timing is measured from the 50% voltage points)
DS005671-50
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DS005671-51


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Timing Diagrams (All timing is measured from the 50% voltage points) (Continued)
Output Enable and Reset with INTR
Note: Read strobe must occur 8 clock periods (8/fCLK) after assertion of interrupt to guarantee reset of INTR .
Typical Applications
DS005671-52
6800 Interface
Ratiometeric with Full-Scale Adjust
DS005671-53
Note: before using caps at VIN or VREF/2,
see section 2.3.2 Input Bypass Capacitors.
DS005671-54
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Typical Applications (Continued)
Absolute with a 2.500V Reference
Absolute with a 5V Reference
*For low power, see also LM385–2.5
DS005671-55
Zero-Shift and Span Adjust: 2V VIN 5V
DS005671-56
Span Adjust: 0V VIN 3V
DS005671-57
DS005671-58
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Typical Applications (Continued)
Directly Converting a Low-Level Signal
A µP Interfaced Comparator
VREF/2=256 mV
DS005671-59
For:
VIN(+)>VIN(−)
Output=FFHEX
For:
VIN(+)<VIN(−)
Output=00HEX
1 mV Resolution with µP Controlled Range
DS005671-60
VREF/2=128 mV
1 LSB=1 mV
VDACVIN(VDAC+256 mV)
0 VDAC < 2.5V
DS005671-61
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Typical Applications (Continued)
Digitizing a Current Flow
Self-Clocking Multiple A/Ds
DS005671-62
External Clocking
* Use a large R value
to reduce loading
at CLK R output.
100 kHzfCLK1460 kHz
DS005671-64
DS005671-63
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Typical Applications (Continued)
Self-Clocking in Free-Running Mode
µP Interface for Free-Running A/D
DS005671-65
*After power-up, a momentary grounding of the WR input is needed to
guarantee operation.
Operating with “Automotive” Ratiometric Transducers
DS005671-66
Ratiometric with VREF/2 Forced
*VIN(−)=0.15 VCC
15% of VCCVXDR85% of VCC
DS005671-67
DS005671-68
µP Compatible Differential-Input Comparator with Pre-Set VOS (with or without Hysteresis)
*See Figure 5 to select R value
DB7=“1” for VIN(+)>VIN(−)+(VREF/2)
Omit circuitry within the dotted area if
hysteresis is not needed
11
DS005671-69
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Typical Applications (Continued)
Handling ±10V Analog Inputs
Low-Cost, µP Interfaced, Temperature-to-Digital
Converter
*Beckman Instruments #694-3-R10K resistor array
DS005671-70
µP Interfaced Temperature-to-Digital Converter
DS005671-71
*Circuit values shown are for 0˚CTA+128˚C
***Can calibrate each sensor to allow easy replacement, then A/D can be calibrated with a pre-set input voltage.
DS005671-72
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Typical Applications (Continued)
Handling ±5V Analog Inputs
Read-Only Interface
*Beckman Instruments #694-3-R10K resistor array
µP Interfaced Comparator with Hysteresis
DS005671-33
Protecting the Input
DS005671-34
Diodes are 1N914
DS005671-35
DS005671-9
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Typical Applications (Continued)
Analog Self-Test for a System
DS005671-36
A Low-Cost, 3-Decade Logarithmic Converter
*LM389 transistors
A, B, C, D = LM324A quad op amp
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DS005671-37


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Typical Applications (Continued)
3-Decade Logarithmic A/D Converter
Noise Filtering the Analog Input
DS005671-73
Multiplexing Differential Inputs
DS005671-74
fC=20 Hz
Uses Chebyshev implementation for steeper roll-off unity-gain, 2nd order,
low-pass filter
Adding a separate filter for each channel increases system response time
if an analog multiplexer is used
DS005671-75
Output Buffers with A/D Data Enabled
Increasing Bus Drive and/or Reducing Time on Bus
DS005671-76
*A/D output data is updated 1 CLK period prior to assertion of INTR
DS005671-77
*Allows output data to set-up at falling edge of CS
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Typical Applications (Continued)
Sampling an AC Input Signal
DS005671-78
Note 11: Oversample whenever possible [keep fs > 2f(−60)] to eliminate input frequency folding (aliasing) and to allow for the skirt response of the filter.
Note 12: Consider the amplitude errors which are introduced within the passband of the filter.
70% Power Savings by Clock Gating
(Complete shutdown takes 30 seconds.)
DS005671-79
Power Savings by A/D and VREF Shutdown
*Use ADC0801, 02, 03 or 05 for lowest power consumption.
Note: Logic inputs can be driven to VCC with A/D supply at zero volts.
Buffer prevents data bus from overdriving output of A/D when in shutdown mode.
Functional Description
1.0 UNDERSTANDING A/D ERROR SPECS
A perfect A/D transfer characteristic (staircase waveform) is
shown in Figure 1. The horizontal scale is analog input volt-
age and the particular points labeled are in steps of 1 LSB
(19.53 mV with 2.5V tied to the VREF/2 pin). The digital out-
put codes that correspond to these inputs are shown as D−1,
D, and D+1. For the perfect A/D, not only will center-value
DS005671-80
(A−1, A, A+1, . . . . ) analog inputs produce the correct out-
put digital codes, but also each riser (the transitions between
adjacent output codes) will be located ±12 LSB away from
each center-value. As shown, the risers are ideal and have
no width. Correct digital output codes will be provided for a
range of analog input voltages that extend ±12 LSB from the
ideal center-values. Each tread (the range of analog input
voltage that provides the same digital output code) is there-
fore 1 LSB wide.
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Functional Description (Continued)
Figure 2 shows a worst case error plot for the ADC0801. All
center-valued inputs are guaranteed to produce the correct
output codes and the adjacent risers are guaranteed to be
no closer to the center-value points than ±14 LSB. In other
words, if we apply an analog input equal to the center-value
±14 LSB, we guarantee that the A/D will produce the correct
digital code. The maximum range of the position of the code
transition is indicated by the horizontal arrow and it is guar-
anteed to be no more than 12 LSB.
The error curve of Figure 3 shows a worst case error plot for
the ADC0802. Here we guarantee that if we apply an analog
input equal to the LSB analog voltage center-value the A/D
will produce the correct digital code.
Transfer Function
Next to each transfer function is shown the corresponding
error plot. Many people may be more familiar with error plots
than transfer functions. The analog input voltage to the A/D
is provided by either a linear ramp or by the discrete output
steps of a high resolution DAC. Notice that the error is con-
tinuously displayed and includes the quantization uncertainty
of the A/D. For example the error at point 1 of Figure 1 is +12
LSB because the digital code appeared 12 LSB in advance
of the center-value of the tread. The error plots always have
a constant negative slope and the abrupt upside steps are
always 1 LSB in magnitude.
Error Plot
DS005671-81
FIGURE 1. Clarifying the Error Specs of an A/D Converter
Accuracy=±0 LSB: A Perfect A/D
Transfer Function
Error Plot
DS005671-82
DS005671-83
FIGURE 2. Clarifying the Error Specs of an A/D Converter
Accuracy=±14 LSB
DS005671-84
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Functional Description (Continued)
Transfer Function
Error Plot
DS005671-85
DS005671-86
FIGURE 3. Clarifying the Error Specs of an A/D Converter
Accuracy=±12 LSB
2.0 FUNCTIONAL DESCRIPTION
The ADC0801 series contains a circuit equivalent of the
256R network. Analog switches are sequenced by succes-
sive approximation logic to match the analog difference input
voltage [VIN(+) − VIN(−)] to a corresponding tap on the R net-
work. The most significant bit is tested first and after 8 com-
parisons (64 clock cycles) a digital 8-bit binary code (1111
1111 = full-scale) is transferred to an output latch and then
an interrupt is asserted (INTR makes a high-to-low transi-
tion). A conversion in process can be interrupted by issuing a
second start command. The device may be operated in the
free-running mode by connecting INTR to the WR input with
CS =0. To ensure start-up under all possible conditions, an
external WR pulse is required during the first power-up
cycle.
On the high-to-low transition of the WR input the internal
SAR latches and the shift register stages are reset. As long
as the CS input and WR input remain low, the A/D will remain
in a reset state. Conversion will start from 1 to 8 clock peri-
ods after at least one of these inputs makes a low-to-high
transition.
A functional diagram of the A/D converter is shown in Figure
4. All of the package pinouts are shown and the major logic
control paths are drawn in heavier weight lines.
The converter is started by having CS and WR simulta-
neously low. This sets the start flip-flop (F/F) and the result-
ing “1” level resets the 8-bit shift register, resets the Interrupt
(INTR) F/F and inputs a “1” to the D flop, F/F1, which is at the
input end of the 8-bit shift register. Internal clock signals then
transfer this “1” to the Q output of F/F1. The AND gate, G1,
combines this “1” output with a clock signal to provide a reset
signal to the start F/F. If the set signal is no longer present
(either WR or CS is a “1”) the start F/F is reset and the 8-bit
shift register then can have the “1” clocked in, which starts
the conversion process. If the set signal were to still be
present, this reset pulse would have no effect (both outputs
of the start F/F would momentarily be at a “1” level) and the
8-bit shift register would continue to be held in the reset
mode. This logic therefore allows for wide CS and WR sig-
nals and the converter will start after at least one of these
signals returns high and the internal clocks again provide a
reset signal for the start F/F.
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Functional Description (Continued)
Note 13: CS shown twice for clarity.
Note 14: SAR = Successive Approximation Register.
DS005671-13
FIGURE 4. Block Diagram
After the “1” is clocked through the 8-bit shift register (which
completes the SAR search) it appears as the input to the
D-type latch, LATCH 1. As soon as this “1” is output from the
shift register, the AND gate, G2, causes the new digital word
to transfer to the TRI-STATE output latches. When LATCH 1
is subsequently enabled, the Q output makes a high-to-low
transition which causes the INTR F/F to set. An inverting
buffer then supplies the INTR input signal.
Note that this SET control of the INTR F/F remains low for 8
of the external clock periods (as the internal clocks run at 18
of the frequency of the external clock). If the data output is
continuously enabled (CS and RD both held low), the INTR
output will still signal the end of conversion (by a high-to-low
transition), because the SET input can control the Q output
of the INTR F/F even though the RESET input is constantly
at a “1” level in this operating mode. This INTR output will
therefore stay low for the duration of the SET signal, which is
8 periods of the external clock frequency (assuming the A/D
is not started during this interval).
When operating in the free-running or continuous conversion
mode (INTR pin tied to WR and CS wired low — see also
section 2.8), the START F/F is SET by the high-to-low tran-
sition of the INTR signal. This resets the SHIFT REGISTER
which causes the input to the D-type latch, LATCH 1, to go
low. As the latch enable input is still present, the Q output will
go high, which then allows the INTR F/F to be RESET. This
reduces the width of the resulting INTR output pulse to only
a few propagation delays (approximately 300 ns).
When data is to be read, the combination of both CS and RD
being low will cause the INTR F/F to be reset and the
TRI-STATE output latches will be enabled to provide the 8-bit
digital outputs.
2.1 Digital Control Inputs
The digital control inputs (CS, RD, and WR) meet standard
T2L logic voltage levels. These signals have been renamed
when compared to the standard A/D Start and Output Enable
labels. In addition, these inputs are active low to allow an
easy interface to microprocessor control busses. For
non-microprocessor based applications, the CS input (pin 1)
can be grounded and the standard A/D Start function is ob-
tained by an active low pulse applied at the WR input (pin 3)
and the Output Enable function is caused by an active low
pulse at the RD input (pin 2).
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Functional Description (Continued)
2.2 Analog Differential Voltage Inputs and
Common-Mode Rejection
This A/D has additional applications flexibility due to the ana-
log differential voltage input. The VIN(−) input (pin 7) can be
used to automatically subtract a fixed voltage value from the
input reading (tare correction). This is also useful in 4 mA–20
mA current loop conversion. In addition, common-mode
noise can be reduced by use of the differential input.
The time interval between sampling VIN(+) and VIN(−) is 4-12
clock periods. The maximum error voltage due to this slight
time difference between the input voltage samples is given
by:
where:
Ve is the error voltage due to sampling delay
VP is the peak value of the common-mode voltage
fcm is the common-mode frequency
As an example, to keep this error to 14 LSB (5 mV) when
operating with a 60 Hz common-mode frequency, fcm, and
using a 640 kHz A/D clock, fCLK, would allow a peak value of
the common-mode voltage, VP, which is given by:
or
which gives
VP1.9V.
The allowed range of analog input voltages usually places
more severe restrictions on input common-mode noise lev-
els.
An analog input voltage with a reduced span and a relatively
large zero offset can be handled easily by making use of the
differential input (see section 2.4 Reference Voltage).
2.3 Analog Inputs
2.3 1 Input Current
Normal Mode
Due to the internal switching action, displacement currents
will flow at the analog inputs. This is due to on-chip stray ca-
pacitance to ground as shown in Figure 5.
DS005671-14
rON of SW 1 and SW 2 5 k
r=rON CSTRAY 5 kx 12 pF = 60 ns
FIGURE 5. Analog Input Impedance
The voltage on this capacitance is switched and will result in
currents entering the VIN(+) input pin and leaving the VIN(−)
input which will depend on the analog differential input volt-
age levels. These current transients occur at the leading
edge of the internal clocks. They rapidly decay and do not
cause errors as the on-chip comparator is strobed at the end
of the clock period.
Fault Mode
If the voltage source applied to the VIN(+) or VIN(−) pin ex-
ceeds the allowed operating range of VCC+50 mV, large in-
put currents can flow through a parasitic diode to the VCC
pin. If these currents can exceed the 1 mA max allowed
spec, an external diode (1N914) should be added to bypass
this current to the VCC pin (with the current bypassed with
this diode, the voltage at the VIN(+) pin can exceed the VCC
voltage by the forward voltage of this diode).
2.3.2 Input Bypass Capacitors
Bypass capacitors at the inputs will average these charges
and cause a DC current to flow through the output resis-
tances of the analog signal sources. This charge pumping
action is worse for continuous conversions with the VIN(+) in-
put voltage at full-scale. For continuous conversions with a
640 kHz clock frequency with the VIN(+) input at 5V, this DC
current is at a maximum of approximately 5 µA. Therefore,
bypass capacitors should not be used at the analog inputs or
the VREF/2 pin for high resistance sources (> 1 k). If input
bypass capacitors are necessary for noise filtering and high
source resistance is desirable to minimize capacitor size, the
detrimental effects of the voltage drop across this input resis-
tance, which is due to the average value of the input current,
can be eliminated with a full-scale adjustment while the
given source resistor and input bypass capacitor are both in
place. This is possible because the average value of the in-
put current is a precise linear function of the differential input
voltage.
2.3.3 Input Source Resistance
Large values of source resistance where an input bypass ca-
pacitor is not used, will not cause errors as the input currents
settle out prior to the comparison time. If a low pass filter is
required in the system, use a low valued series resistor
(1 k) for a passive RC section or add an op amp RC ac-
tive low pass filter. For low source resistance applications,
(1 k), a 0.1 µF bypass capacitor at the inputs will prevent
noise pickup due to series lead inductance of a long wire. A
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Functional Description (Continued)
100series resistor can be used to isolate this
capacitor — both the R and C are placed outside the feed-
back loop — from the output of an op amp, if used.
2.3.4 Noise
The leads to the analog inputs (pins 6 and 7) should be kept
as short as possible to minimize input noise coupling. Both
noise and undesired digital clock coupling to these inputs
can cause system errors. The source resistance for these in-
puts should, in general, be kept below 5 k. Larger values of
source resistance can cause undesired system noise
pickup. Input bypass capacitors, placed from the analog in-
puts to ground, will eliminate system noise pickup but can
create analog scale errors as these capacitors will average
the transient input switching currents of the A/D (see section
2.3.1.). This scale error depends on both a large source re-
sistance and the use of an input bypass capacitor. This error
can be eliminated by doing a full-scale adjustment of the A/D
(adjust VREF/2 for a proper full-scale reading — see section
2.5.2 on Full-Scale Adjustment) with the source resistance
and input bypass capacitor in place.
2.4 Reference Voltage
2.4.1 Span Adjust
For maximum applications flexibility, these A/Ds have been
designed to accommodate a 5 VDC, 2.5 VDC or an adjusted
voltage reference. This has been achieved in the design of
the IC as shown in Figure 6.
DS005671-15
FIGURE 6. The VREFERENCE Design on the IC
Notice that the reference voltage for the IC is either 12 of the
voltage applied to the VCC supply pin, or is equal to the volt-
age that is externally forced at the VREF/2 pin. This allows for
a ratiometric voltage reference using the VCC supply, a 5
VDC reference voltage can be used for the VCC supply or a
voltage less than 2.5 VDC can be applied to the VREF/2 input
for increased application flexibility. The internal gain to the
VREF/2 input is 2, making the full-scale differential input volt-
age twice the voltage at pin 9.
An example of the use of an adjusted reference voltage is to
accommodate a reduced span — or dynamic voltage range
of the analog input voltage. If the analog input voltage were
to range from 0.5 VDC to 3.5 VDC, instead of 0V to 5 VDC, the
span would be 3V as shown in Figure 7. With 0.5 VDC ap-
plied to the VIN(−) pin to absorb the offset, the reference volt-
age can be made equal to 12 of the 3V span or 1.5 VDC. The
A/D now will encode the VIN(+) signal from 0.5V to 3.5 V with
the 0.5V input corresponding to zero and the 3.5 VDC input
corresponding to full-scale. The full 8 bits of resolution are
therefore applied over this reduced analog input voltage
range.
2.4.2 Reference Accuracy Requirements
The converter can be operated in a ratiometric mode or an
absolute mode. In ratiometric converter applications, the
magnitude of the reference voltage is a factor in both the out-
put of the source transducer and the output of the A/D con-
verter and therefore cancels out in the final digital output
code. The ADC0805 is specified particularly for use in ratio-
metric applications with no adjustments required. In absolute
conversion applications, both the initial value and the tem-
perature stability of the reference voltage are important fac-
tors in the accuracy of the A/D converter. For VREF/2 volt-
ages of 2.4 VDC nominal value, initial errors of ±10 mVDC will
cause conversion errors of ±1 LSB due to the gain of 2 of the
VREF/2 input. In reduced span applications, the initial value
and the stability of the VREF/2 input voltage become even
more important. For example, if the span is reduced to 2.5V,
the analog input LSB voltage value is correspondingly re-
duced from 20 mV (5V span) to 10 mV and 1 LSB at the
VREF/2 input becomes 5 mV. As can be seen, this reduces
the allowed initial tolerance of the reference voltage and re-
quires correspondingly less absolute change with tempera-
ture variations. Note that spans smaller than 2.5V place
even tighter requirements on the initial accuracy and stability
of the reference source.
In general, the magnitude of the reference voltage will re-
quire an initial adjustment. Errors due to an improper value
of reference voltage appear as full-scale errors in the A/D
transfer function. IC voltage regulators may be used for ref-
erences if the ambient temperature changes are not exces-
sive. The LM336B 2.5V IC reference diode (from National
Semiconductor) has a temperature stability of 1.8 mV typ
(6 mV max) over 0˚CTA+70˚C. Other temperature range
parts are also available.
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Functional Description (Continued)
DS005671-87
a) Analog Input Signal Example
DS005671-88
*Add if VREF/2 1 VDC with LM358 to draw 3 mA to ground.
b) Accommodating an Analog Input from
0.5V (Digital Out = 00HEX) to 3.5V
(Digital Out=FFHEX)
FIGURE 7. Adapting the A/D Analog Input Voltages to Match an Arbitrary Input Signal Range
2.5 Errors and Reference Voltage Adjustments
2.5.1 Zero Error
The zero of the A/D does not require adjustment. If the mini-
mum analog input voltage value, VIN(MIN), is not ground, a
zero offset can be done. The converter can be made to out-
put 0000 0000 digital code for this minimum input voltage by
biasing the A/D VIN(−) input at this VIN(MIN) value (see Appli-
cations section). This utilizes the differential mode operation
of the A/D.
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the VIN (−) input and applying a small magnitude
positive voltage to the VIN (+) input. Zero error is the differ-
ence between the actual DC input voltage that is necessary
to just cause an output digital code transition from 0000 0000
to 0000 0001 and the ideal 12 LSB value (12 LSB = 9.8 mV
for VREF/2=2.500 VDC).
is applied to pin 6 and the zero reference voltage at pin 7
should then be adjusted to just obtain the 00HEX to 01HEX
code transition.
The full-scale adjustment should then be made (with the
proper VIN(−) voltage applied) by forcing a voltage to the
VIN(+) input which is given by:
where:
VMAX=The high end of the analog input range
and
VMIN=the low end (the offset zero) of the analog range.
(Both are ground referenced.)
The VREF/2 (or VCC) voltage is then adjusted to provide a
code change from FEHEX to FFHEX. This completes the ad-
justment procedure.
2.5.2 Full-Scale
The full-scale adjustment can be made by applying a differ-
ential input voltage that is 112 LSB less than the desired ana-
log full-scale voltage range and then adjusting the magni-
tude of the VREF/2 input (pin 9 or the VCC supply if pin 9 is
not used) for a digital output code that is just changing from
1111 1110 to 1111 1111.
2.6 Clocking Option
The clock for the A/D can be derived from the CPU clock or
an external RC can be added to provide self-clocking. The
CLK IN (pin 4) makes use of a Schmitt trigger as shown in
Figure 8.
2.5.3 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
that does not go to ground) this new zero reference should
be properly adjusted first. A VIN(+) voltage that equals this
desired zero reference plus 12 LSB (where the LSB is calcu-
lated for the desired analog span, 1 LSB=analog span/256)
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Functional Description (Continued)
DS005671-17
FIGURE 8. Self-Clocking the A/D
Heavy capacitive or DC loading of the clock R pin should be
avoided as this will disturb normal converter operation.
Loads less than 50 pF, such as driving up to 7 A/D converter
clock inputs from a single clock R pin of 1 converter, are al-
lowed. For larger clock line loading, a CMOS or low power
TTL buffer or PNP input logic should be used to minimize the
loading on the clock R pin (do not use a standard TTL
buffer).
2.7 Restart During a Conversion
If the A/D is restarted (CS and WR go low and return high)
during a conversion, the converter is reset and a new con-
version is started. The output data latch is not updated if the
conversion in process is not allowed to be completed, there-
fore the data of the previous conversion remains in this latch.
The INTR output simply remains at the “1” level.
2.8 Continuous Conversions
For operation in the free-running mode an initializing pulse
should be used, following power-up, to ensure circuit opera-
tion. In this application, the CS input is grounded and the WR
input is tied to the INTR output. This WR and INTR node
should be momentarily forced to logic low following a
power-up cycle to guarantee operation.
2.9 Driving the Data Bus
This MOS A/D, like MOS microprocessors and memories,
will require a bus driver when the total capacitance of the
data bus gets large. Other circuitry, which is tied to the data
bus, will add to the total capacitive loading, even in
TRI-STATE (high impedance mode). Backplane bussing
also greatly adds to the stray capacitance of the data bus.
There are some alternatives available to the designer to
handle this problem. Basically, the capacitive loading of the
data bus slows down the response time, even though DC
specifications are still met. For systems operating with a
relatively slow CPU clock frequency, more time is available
in which to establish proper logic levels on the bus and there-
fore higher capacitive loads can be driven (see typical char-
acteristics curves).
At higher CPU clock frequencies time can be extended for
I/O reads (and/or writes) by inserting wait states (8080) or
using clock extending circuits (6800).
Finally, if time is short and capacitive loading is high, external
bus drivers must be used. These can be TRI-STATE buffers
(low power Schottky such as the DM74LS240 series is rec-
ommended) or special higher drive current products which
are designed as bus drivers. High current bipolar bus drivers
with PNP inputs are recommended.
2.10 Power Supplies
Noise spikes on the VCC supply line can cause conversion
errors as the comparator will respond to this noise. A low in-
ductance tantalum filter capacitor should be used close to
the converter VCC pin and values of 1 µF or greater are rec-
ommended. If an unregulated voltage is available in the sys-
tem, a separate LM340LAZ-5.0, TO-92, 5V voltage regulator
for the converter (and other analog circuitry) will greatly re-
duce digital noise on the VCC supply.
2.11 Wiring and Hook-Up Precautions
Standard digital wire wrap sockets are not satisfactory for
breadboarding this A/D converter. Sockets on PC boards
can be used and all logic signal wires and leads should be
grouped and kept as far away as possible from the analog
signal leads. Exposed leads to the analog inputs can cause
undesired digital noise and hum pickup, therefore shielded
leads may be necessary in many applications.
A single point analog ground that is separate from the logic
ground points should be used. The power supply bypass ca-
pacitor and the self-clocking capacitor (if used) should both
be returned to digital ground. Any VREF/2 bypass capacitors,
analog input filter capacitors, or input signal shielding should
be returned to the analog ground point. A test for proper
grounding is to measure the zero error of the A/D converter.
Zero errors in excess of 14 LSB can usually be traced to im-
proper board layout and wiring (see section 2.5.1 for mea-
suring the zero error).
3.0 TESTING THE A/D CONVERTER
There are many degrees of complexity associated with test-
ing an A/D converter. One of the simplest tests is to apply a
known analog input voltage to the converter and use LEDs to
display the resulting digital output code as shown in Figure 9.
For ease of testing, the VREF/2 (pin 9) should be supplied
with 2.560 VDC and a VCC supply voltage of 5.12 VDC should
be used. This provides an LSB value of 20 mV.
If a full-scale adjustment is to be made, an analog input volt-
age of 5.090 VDC (5.120–112 LSB) should be applied to the
VIN(+) pin with the VIN(−) pin grounded. The value of the
VREF/2 input voltage should then be adjusted until the digital
output code is just changing from 1111 1110 to 1111 1111.
This value of VREF/2 should then be used for all the tests.
The digital output LED display can be decoded by dividing
the 8 bits into 2 hex characters, the 4 most significant (MS)
and the 4 least significant (LS). Table 1 shows the fractional
binary equivalent of these two 4-bit groups. By adding the
voltages obtained from the “VMS” and “VLS” columns in
Table 1, the nominal value of the digital display (when
VREF/2 = 2.560V) can be determined. For example, for an
output LED display of 1011 0110 or B6 (in hex), the voltage
values from the table are 3.520 + 0.120 or 3.640 VDC. These
voltage values represent the center-values of a perfect A/D
converter. The effects of quantization error have to be ac-
counted for in the interpretation of the test results.
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Functional Description (Continued)
DS005671-18
FIGURE 9. Basic A/D Tester
For a higher speed test system, or to obtain plotted data, a
digital-to-analog converter is needed for the test set-up. An
accurate 10-bit DAC can serve as the precision voltage
source for the A/D. Errors of the A/D under test can be ex-
pressed as either analog voltages or differences in 2 digital
words.
A basic A/D tester that uses a DAC and provides the error as
an analog output voltage is shown in Figure 8. The 2 op
amps can be eliminated if a lab DVM with a numerical sub-
traction feature is available to read the difference voltage,
“A–C”, directly. The analog input voltage can be supplied by
a low frequency ramp generator and an X-Y plotter can be
used to provide analog error (Y axis) versus analog input (X
axis).
For operation with a microprocessor or a computer-based
test system, it is more convenient to present the errors digi-
tally. This can be done with the circuit of Figure 11, where the
output code transitions can be detected as the 10-bit DAC is
incremented. This provides 14 LSB steps for the 8-bit A/D un-
der test. If the results of this test are automatically plotted
with the analog input on the X axis and the error (in LSB’s)
as the Y axis, a useful transfer function of the A/D under test
results. For acceptance testing, the plot is not necessary and
the testing speed can be increased by establishing internal
limits on the allowed error for each code.
4.0 MICROPROCESSOR INTERFACING
To dicuss the interface with 8080A and 6800 microproces-
sors, a common sample subroutine structure is used. The
microprocessor starts the A/D, reads and stores the results
of 16 successive conversions, then returns to the user’s pro-
gram. The 16 data bytes are stored in 16 successive
memory locations. All Data and Addresses will be given in
hexadecimal form. Software and hardware details are pro-
vided separately for each type of microprocessor.
4.1 Interfacing 8080 Microprocessor Derivatives (8048,
8085)
This converter has been designed to directly interface with
derivatives of the 8080 microprocessor. The A/D can be
mapped into memory space (using standard memory ad-
dress decoding for CS and the MEMR and MEMW strobes)
or it can be controlled as an I/O device by using the I/O R
and I/O W strobes and decoding the address bits A0 A7
(or address bits A8 A15 as they will contain the same 8-bit
address information) to obtain the CS input. Using the I/O
space provides 256 additional addresses and may allow a
simpler 8-bit address decoder but the data can only be input
to the accumulator. To make use of the additional memory
reference instructions, the A/D should be mapped into
memory space. An example of an A/D in I/O space is shown
in Figure 12.
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Functional Description (Continued)
DS005671-89
FIGURE 10. A/D Tester with Analog Error Output
HEX
BINARY
FIGURE 11. Basic “Digital” A/D Tester
DS005671-90
TABLE 1. DECODING THE DIGITAL OUTPUT LEDs
FRACTIONAL BINARY VALUE FOR
MS GROUP
LS GROUP
F 1111
E 1110
D 1101
C 1100
3/4
B 1011
A 1010
9 1001
8 1 0 0 0 1/2
7 0111
6 0110
5 0101
4 0100
1/4
3 0011
2 0010
1 0001
0 0000
Note 15: Display Output=VMS Group + VLS Group
7/8
5/8
3/8
1/8
15/16
13/16
11/16
9/16
7/16
5/16
3/16
1/16
1/32
3/64
1/64
7/128
5/128
3/128
1/128
15/256
13/256
11/256
9/256
7/256
2/256
3/256
1/256
OUTPUT VOLTAGE
CENTER VALUES
WITH
VREF/2=2.560 VDC
VMS
VLS
GROUP
GROUP
(Note 15)
(Note 15)
4.800
0.300
4.480
0.280
4.160
0.260
3.840
0.240
3.520
0.220
3.200
0.200
2.880
0.180
2.560
0.160
2.240
0.140
1.920
0.120
1.600
0.100
1.280
0.080
0.960
0.060
0.640
0.040
0.320
0.020
00
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Functional Description (Continued)
Note 16: *Pin numbers for the DP8228 system controller, others are INS8080A.
Note 17: Pin 23 of the INS8228 must be tied to +12V through a 1 kresistor to generate the RST 7
instruction when an interrupt is acknowledged as required by the accompanying sample program.
FIGURE 12. ADC0801_INS8080A CPU Interface
DS005671-20
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Functional Description (Continued)
SAMPLE PROGRAM FOR Figure 12 ADC0801–INS8080A CPU INTERFACE
DS005671-99
Note 18: The stack pointer must be dimensioned because a RST 7 instruction pushes the PC onto the stack.
Note 19: All address used were arbitrarily chosen.
The standard control bus signals of the 8080 CS, RD and
WR) can be directly wired to the digital control inputs of the
A/D and the bus timing requirements are met to allow both
starting the converter and outputting the data onto the data
bus. A bus driver should be used for larger microprocessor
systems where the data bus leaves the PC board and/or
must drive capacitive loads larger than 100 pF.
4.1.1 Sample 8080A CPU Interfacing Circuitry and
Program
The following sample program and associated hardware
shown in Figure 12 may be used to input data from the con-
verter to the INS8080A CPU chip set (comprised of the
INS8080A microprocessor, the INS8228 system controller
and the INS8224 clock generator). For simplicity, the A/D is
controlled as an I/O device, specifically an 8-bit bi-directional
port located at an arbitrarily chosen port address, E0. The
TRI-STATE output capability of the A/D eliminates the need
for a peripheral interface device, however address decoding
is still required to generate the appropriate CS for the con-
verter.
It is important to note that in systems where the A/D con-
verter is 1-of-8 or less I/O mapped devices, no address de-
coding circuitry is necessary. Each of the 8 address bits (A0
to A7) can be directly used as CS inputs — one for each I/O
device.
4.1.2 INS8048 Interface
The INS8048 interface technique with the ADC0801 series
(see Figure 13) is simpler than the 8080A CPU interface.
There are 24 I/O lines and three test input lines in the 8048.
With these extra I/O lines available, one of the I/O lines (bit
0 of port 1) is used as the chip select signal to the A/D, thus
eliminating the use of an external address decoder. Bus con-
trol signals RD, WR and INT of the 8048 are tied directly to
the A/D. The 16 converted data words are stored at on-chip
RAM locations from 20 to 2F (Hex). The RD and WR signals
are generated by reading from and writing into a dummy ad-
dress, respectively. A sample interface program is shown
below.
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Functional Description (Continued)
FIGURE 13. INS8048 Interface
DS005671-21
SAMPLE PROGRAM FOR Figure 13 INS8048 INTERFACE
4.2 Interfacing the Z-80
The Z-80 control bus is slightly different from that of the
8080. General RD and WR strobes are provided and sepa-
rate memory request, MREQ, and I/O request, IORQ, sig-
nals are used which have to be combined with the general-
ized strobes to provide the equivalent 8080 signals. An
advantage of operating the A/D in I/O space with the Z-80 is
that the CPU will automatically insert one wait state (the RD
and WR strobes are extended one clock period) to allow
more time for the I/O devices to respond. Logic to map the
A/D in I/O space is shown in Figure 14.
DS005671-A0
DS005671-23
FIGURE 14. Mapping the A/D as an I/O Device
for Use with the Z-80 CPU
Additional I/O advantages exist as software DMA routines
are available and use can be made of the output data trans-
fer which exists on the upper 8 address lines (A8 to A15) dur-
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Functional Description (Continued)
ing I/O input instructions. For example, MUX channel selec-
tion for the A/D can be accomplished with this operating
mode.
4.3 Interfacing 6800 Microprocessor Derivatives
(6502, etc.)
The control bus for the 6800 microprocessor derivatives
does not use the RD and WR strobe signals. Instead it em-
ploys a single R/W line and additional timing, if needed, can
be derived fom the φ2 clock. All I/O devices are memory
mapped in the 6800 system, and a special signal, VMA, indi-
cates that the current address is valid. Figure 15 shows an
interface schematic where the A/D is memory mapped in the
6800 system. For simplicity, the CS decoding is shown using
12 DM8092. Note that in many 6800 systems, an already de-
coded 4/5 line is brought out to the common bus at pin 21.
This can be tied directly to the CS pin of the A/D, provided
that no other devices are addressed at HX ADDR: 4XXX or
5XXX.
The following subroutine performs essentially the same func-
tion as in the case of the 8080A interface and it can be called
from anywhere in the user’s program.
In Figure 16 the ADC0801 series is interfaced to the M6800
microprocessor through (the arbitrarily chosen) Port B of the
MC6820 or MC6821 Peripheral Interface Adapter, (PIA).
Here the CS pin of the A/D is grounded since the PIA is al-
ready memory mapped in the M6800 system and no CS de-
coding is necessary. Also notice that the A/D output data
lines are connected to the microprocessor bus under pro-
gram control through the PIA and therefore the A/D RD pin
can be grounded.
A sample interface program equivalent to the previous one is
shown below Figure 16. The PIA Data and Control Registers
of Port B are located at HEX addresses 8006 and 8007, re-
spectively.
5.0 GENERAL APPLICATIONS
The following applications show some interesting uses for
the A/D. The fact that one particular microprocessor is used
is not meant to be restrictive. Each of these application cir-
cuits would have its counterpart using any microprocessor
that is desired.
5.1 Multiple ADC0801 Series to MC6800 CPU Interface
To transfer analog data from several channels to a single mi-
croprocessor system, a multiple converter scheme presents
several advantages over the conventional multiplexer
single-converter approach. With the ADC0801 series, the dif-
ferential inputs allow individual span adjustment for each
channel. Furthermore, all analog input channels are sensed
simultaneously, which essentially divides the microproces-
sor’s total system servicing time by the number of channels,
since all conversions occur simultaneously. This scheme is
shown in Figure 17.
Note 20: Numbers in parentheses refer to MC6800 CPU pin out.
Note 21: Number or letters in brackets refer to standard M6800 system common bus code.
FIGURE 15. ADC0801-MC6800 CPU Interface
DS005671-24
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Functional Description (Continued)
SAMPLE PROGRAM FOR Figure 15 ADC0801-MC6800 CPU INTERFACE
DS005671-A1
Note 22: In order for the microprocessor to service subroutines and interrupts, the stack pointer must be dimensioned in the user’s program.
FIGURE 16. ADC0801–MC6820 PIA Interface
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