TC518128BFL-10V Datasheet PDF
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TOSHIBA
SILICON GATE CMOS
TC518l28BPL/BFL/BFWL/BFIL-70V/80V/lOV
131,072 WORD x 8 BIT CMOS PSEUDO STATIC RAM
Description
The TC518128B-V is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518128B-V
utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power
storage. The TC518128B-Voperates from a single power supply of 2.7 - 5.5V. Refreshing is supported by a refresh (RFS~ input
which enables two types of refreshing - auto refresh and self refresh. The TC518128B-V features a static RAM-like interface with a
write cycle in which the input data is written into the memory cell at the rising edge of RMI thus simplifying the microprocessor
interface.
The TC518128B-V is pin-compatible with the 1M bit CMOS static RAM JEDEC standard and is available in a 32-pin, 0.6 inch
width plastic DIP, a small outline plastic flat package, and a 32-pin thin small outline plastic package (forward type).
Features
Pin Connection (Top View)
• Organization:
131,072 words x 8 bits
• Low voltage operation
2.7V - 5.5V
• Data retention supply voltage: 2.7V - 5.5V
• Fast access time
TC518128B-V Family
-70 -80 -10
tCEA CE Access Time
tOEA OE Access Time
tRc Cycle Time
Power Dissipation
Self Refresh Current 1 5.5V
1 3.OV
70ns
25ns
115ns
385mW
SOns
30ns
130ns
330mW
50J.lA
25J.lA
100ns
40ns
160ns
275mW
FsH
A16
A14
A12
A7
A6
AS
A4
A3
A2
Al
AO
1101
1102
1103
GNO
~~~
CE2
RIW
A13
A8
A9
All
OE
AlP
Ce1
1108
1107
1106
1105
1/04
TC518128BPL/BFL/BFVVl
'li 1O 3
:
16 17
TC518128BFTL ( Forward)
• Auto refresh is supported by an internal refresh address
counter
• Self refresh is supported by an internal timer
• Inputs and outputs TTL compatible
• Refresh: 512 refresh cycles/8ms
• Auto refresh power down feature
• Pin compatible: 1M SRAM (JEDEC)
• Package
- TC518128BPL: DIP32-P-600
- TC518128BFL: SOP32-P-450
- TC518128BFWL: SOP32-P-525
- TC518128BFTL: TSOP32-P-0820
Pin Names
AO - A16
R/W
OE
RFSH
CE1, CE2
1/01 - 1/08
Voo
GND
Address Inputs
Read/Write Control Input
Output Enable Input
Refresh Input
Chip Enable Inputs
Data InputslOutputs
Power
Ground
(TSOP)
PIN NO. 1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16
PIN NAME A11 Ag As A13 R/W CE2 A1S Voo RFSH A16 A14 A12 A7 A6 As A4
PIN NO. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN NAME A3 A2 A1 Ao 1/01 1/02 1/03 GND 1/04 1/05 1/06 1/07 1/08 CE1 A10 OE
TOSHIBA AMERICA ELECTRONIC CDMPDNENTS, INC.
0-67


TC518128BFL-10V Datasheet PDF
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TC518128BPUBFUBFWUBFTL-70Vl80Vl10V
Block Diagram
Voo
Static RAM
ROW
ADDRESS
BUFFER (9)
MEMORY
ARRAY
512x256)(8
1/01
S
1/08
CEl
CE2
OEo---+--Q
R/Wo---oQ
Operating Mode
~NMODE
CE1 eE2 OE R/W RFSH AO - A16 1/01 - 8
Read
Write
CE only Refresh
Auto/Self Refresh
Auto/Self Refresh
Standby
Standby
LHL H *
LH* L *
LHH H *
V* OUT
V* IN
V* HZ
H * * * L * HZ
* L * * L * HZ
H * * * H * HZ
* L * * H * HZ
H = High level input (VIH)
L = Low level input (VIU
* = V1H orV1L
V* =At the falling edge of CE1 (CE2 = H) or the rising edge of CE2 (CE1 = L), all address inputs are latched. At all other times, the address inputs are "*".
HZ = High impedance
Maximum Ratings
SYMBOL
ITEM
V IN Input Voltage
VOUT Output Voltage
Voo Power Supply Voltage
TOPR Operating Temperature
TSTRG Storage Temperature
TSOLOER Soldering Temperature • Time
Po Power Dissipation
lOUT Short Circuit Output Current
RATING.
-1.0 - 7.0
. -1.0 - 7.0
-1.0 -7.0
0-70
-55 - 150
260· 10
600
50
UNIT NOTES
V
V
V
°C
°C
°C· sec
mW
mA
1
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Static RAM
TC518128BPUBFUBFWUBFTL-70Vl80Vl10V
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Voo Power Supply Voltage
VIH Input High Voltage
VIL Input Low Voltage
MIN. TYP. MAX. UNIT NOTES
4.5 5.0
5.5
V
2.4 - Voo + 1.0 V
-1.0 - O.B V
2
= =DC Characteristics (Ta 0 - 70°C, Voo 5V±10%)
SYMBOL
PARAMETER
1000
10051
10052
IOOFl
IOOF2
IOOF3
IOOF4
II(L)
10(L)
VOH
VOL
Operating Current (Average)
CE1, CE2, Address cycling: tRC = tRc min.
70ns version
BOns version
1OOns version
Standby Current
CE1 = VIH or CE2 = VIL. RFSH = VIH
Standby Current
CE1 = Voo - 0.2V or CE2 = 0.2V,
RFSH = Voo - 0.2V
Self Refresh Current (Average)
CE1 = V1H or CE2 = V1L,
RFSH = VIL
Self Refresh Current (Average)
CEt = Voo - 0.2V or CE2 = 0.2V,
RFSH = 0.2V
Auto Refresh Current (Average)
RFSH cycling: tFC = tFC min
CE only Refresh Current (Average)
GET, CE2, Address cycling: tRc = tRc min.
70ns version
BOns version
100ns version
Input Leakage Current
OV ~VIN ~ Voo, All other Inputs not under test = OV
Output Leakage Current
Output Disabled (CE1 = VIH or CE2 = VIL or OE = VIH or RIW = Vld,
OV ~ VOUT ~ Voo
Output High Level
10H = -1.0 mA
Output Low Level
10L= 2.1mA
MIN. TYP. MAX. UNIT NOTES
- 50 70
- 40 60 mA 3,4
- 35 50
- - 1 mA
- 35 50 J.lA
- - 1 mA
- 35 50 J.lA
- - 2 mA
- 50 70
- 40 60 mA 3
- 35 50
- - ±10 J.lA
- - ±10 J.lA
2.4 -
--
-V
0.4 V
Note:
For IDDS1 and IDDF1 with CE1 = V1H (CE2 = V1U. the specified limits are guaranteed under the condition CE2 = V1H or CE2 = V1L
(CE1 =V1H or CE1 = V1U.
For IDDS2 and IDDF2 with CE1 ~ VDD - 0.2V (CE2 :s; 0.2V). the specified limits are guaranteed under the condition CE2 ~ VDD - 0.2V or CE2 :s; 0.2V
(CE1 ~ VDD - 0.2V or CE1 :s; 0.2V).
Capacitance* (VOO = 5V, Ta = 25°C, f = 1MHz)
SYMBOL
PARAMETER
Cll Input Capacitance (AO - A16)
CI2 Input Capacitance (GET, CE2, DE, RIW, RFSH)
CIO InpuVOutput Capacitance
*This parameter is periodically sampled and is not 100% tested.
MIN. MAX. UNIT
-5
- 7 pF
-7
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TC518128BPUBFUBFWUBFTL-70VJ80VJ10V
Static RAM
AC Characteristics (Ta = 0 - 70°C, Voo = 5V±10%) (Notes: 5, 6, 7, 8)
SYMBOL
PARAMETER
-70
MIN. MAX.
-80
MIN. MAX.
tRC
tRMW
tCE
tp
tCEA
tOEA
tCLZ
tOLZ
tWLZ
tCHZ
tOHZ
tWHZ
toos
tOOH
tRCS
tRCH
twp
tWCH
tCWL
tosw
tosc
tOHW
tOHc
tAsc
tAHC
tRHC
tFc
tRFO
tFAP
t FP
tFAS
tFRS
tREF
tT
tCES
tCEH
Random Read, Write Cycle Time
Read Modify Write Cycle Time
CE Pulse Width
CE Precharge Time
CE Access Time
C5E Access Time
CE to Output in Low -Z
OE to Output in Low -Z
Output Active from End of Write
Chip Disable to Output in High-Z
C5E Disable to Output in High-Z
Write Enable to Output in High-Z
OE Output Disable Setup Time
OE Output Disable Hold Time
Read Command Setup Time
Read Command Hold Time
Write Pulse Width
Write Command Hold Time
Write Command to CE Lead Time
Data Setup Time from RIW
Data Setup Time from CE
Data Hold Time from RIW
Data Hold Time from CE
Address Setup Time
Address Hold Time
RFSH Command Hold Time
Auto Refresh Cycle Time
RFSH Delay Time from CE
RFSH Pulse Width (Auto Refresh)
RFSH Precharge Time
RFSH Pulse Width (Self Refresh)
CE Delay Time from RFSH (Self Refresh)
Refresh Period (512 cycles, AO - AS)
Transition Time (Rise and Fall)
CE2 Low Setup Time
CE2 Low Hold Time
115
160
70
35
-
-
20
0
0
0
0
0
0
10
0
0
20
35
20
15
15
0
0
0
20
15
115
35
30
30
8,000
160
-
3
5
5
-
-
10,000
-
70
25
-
-
-
20
20
25
-
-
-
-
-
10,000
10,000
-
-
-
-
-
-
-
-
-
8,000
-
-
-
8
50
-
-
130
180
80
40
-
-
20
0
0
0
0
0
0
10
0
0
25
40
25
20
20
0
0
0
25
15
130
40
30
30
8,000
' 160
-
3
5
5
-
-
10,000
-
80
30
-
-
-
20
20
25
-
-
-
-
-
10,000
10,000
-
-
-
-
-
-
-
-
-
8,000
-
-
-
8
50
-
-
-10
MIN.
160
220
100
50
-
-
20
0
0
0
0
0
0
10
0
0
30
50
30
25
25
0
0
0
30
15
160
50
30
30
8,000
190
-
3
5
5
MAX.
-
-
10,000
-
100
40
-
-
-
25
25
30
-
-
-
-
-
10,000
10,000
-
-
-
-
-
-
-
-
-
8,000
-
-
-
8
50
-
-
UNIT NOTES
r----
I----
13
r----
r----
r----
I----
f-------
r----
r----
9
r----
9
r----
9
r----
I----
r----
r----
ns I - - - -
r----
r----
r----
10
f----
10
f----
10
r----
10
I----
11
f----
11
r----
I----
f----
12
r----
12
~
12
~
12
ms
-
ns 14
-
14
0-70
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Static RAM
TC518128BPUBFUBFWUBFTL·70Vl80Vl1 OV
3.0V Operation
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Voo
V 1H
V 1L
Power Supply Voltage
Input High Voltage
Input Low Voltage
MIN.
2.7
Voo - 0.2V
-0.5
TYP. MAX. UNIT NOTES
3.0 3.3
- Voo + 1.0V
- 0.2
V
V
V
2
DC Characteristics (Ta =0 - 70°C, Voo =3.0V±O.3V)
SYMBOL
PARAMETER
1000
100S2
100F2
100F3
100F4
II(L)
10(L)
VOH
VOL
Operating Current (Average)
=CE1, CE2, Address cycling: tRc tRC min.
Standby Current
Self Refresh Current (Average)
Auto Refresh Current (Average)
=RFSH cycling: tFc tFG min
CE only Refresh Current (Average)
=CE1, CE2, Address cycling: tRG tRG min.
Input Leakage Current
=OV::; V1N ::; V oo, All other Inputs not under test OV
Output Leakage Current
Output Disable, OV::; VOUT ::; Voo
Output High Level
10H =-1mA
=10H -100~
Output Low Level
10L =2.1mA
10L = 100/lA
MIN. TYP. MAX.
- 15 20
- 15 25
- 15 25
- -2
- 15 20
- - ±10
-
2.4
Voo - O.2V
-
-
-
-
-
-
-
±10
-
-
0.4
0.2
UNIT NOTES
rnA 3,4
~
~
rnA
rnA 3
~
~
V
V
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TC518128BPUBFUBFWUBFTL·70Vl80Vl1 OV
Static RAM
AC Characteristics (Ta = 0 - 70°C, Voo = 3.0V±O.3V) (Notes: 5, 6, 8)
SYMBOL
PARAMETER
MIN. MAX. UNIT NOTES
tRC
tRMW
tCE
tp
tCEA
tOEA
tCLl
tOll
tWLl
tCHZ
tOHZ
tWHZ
toos
tOOH
tRCS
tRCH
twp
tWCH
tCWL
tosw
tosc
tOHW
tOHC
tASC
tAHC
tRHC
tFC
tRFo
tFAP
tFP
tFAS
tFRS
tREF
tT
tCES
tCEH
Random Read, Write Cycle Time
Read Modify Write Cycle Time
CE Pulse Width
CE Precharge Time
CE Access Time
OE Access Time
CE to Output in Low -Z
OE to Output in Low -Z
Output Active from End of Write
Chip Disable to Output in High-Z
OE Disable to Output in High-Z
Write Enable to Output in High-Z
OE Output Disable Setup Time
OE Output Disable Hold Time
Read Command Setup Time
Read Command Hold Time
Write Pulse Width
Write Command Hold Time
Write Command to CE Lead Time
Data Setup Time from RIW
Data Setup Time from CE
Data Hold Time from RIW
Data Hold Time from CE
Address Setup Time
Address Hold Time
RFSH Command Hold Time
Auto Refresh Cycle Time
RFSH Delay Time from CE
RFSH Pulse Width (Auto Refresh)
RFSH Precharge Time
RFSH Pulse Width (Self Refresh)
CE Delay Time from RFSH (Self Refresh)
Refresh Period (512 cycles, AO - A8)
Transition Time (Rise and Fall)
CE2 Low Setup Time
CE2 Low Hold Time
240
320
150
80
-
-
20
5
5
0
0
0
0
10
0
0
35
70
35
30
30
°
°
°
35
15
240
80
50
50
8,000
300
-
3
10
10
-
-
10,000
-
150
80
-
-
-
30
30
40
-
-
-
-
-
10,000
10,000
-
-
-
-
-
-
-
-
-
8,000
-
-
-
8
50
-
-
f----
f----
13
t----
t----
-
-
-
-
-
9
-
9
-
9
-
-
-
-
ns -
-
-
-
10
-
- 10
- 10
10
r----
11
t----
11
f----
f----
t----
t----
12
f----
12
t----
12
t----
12
ms
t----
ns 14
f----
14
Timing Reference Levels:
Input Reference Levels: 1.5v/1.5V
Output Reference Levels: 1.5V/1.5V
0·72
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TC518128BFL-10V Datasheet PDF
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Static RAM
TC518128BPUBFUBFWUBFTL-70Vl80Vl10V
Notes:
1) Stress greater than those listed under "Maximum Ratings" may cause permanent damage to the device.
2) All voltages are referenced to GND.
3) 1000 and IOOF4 depend on the cycle time.
4) 1000 depends on the output loading. Specified values are obtained with the outputs open.
5) An initial pause of 100llS with high CE1 or low CE2 is required after power-up before proper device operation is achieved.
6) AC measurements assume tT =5ns.
7) Timing reference levels
Input Levels
Input Reference Levels
Output Reference Levels
V1H
V1L
= 2.6V
=0.6V
V1H
V1L
= 2.4V
=0.8V
VOH = 2.2V
VOL = 0.8V
INPUT
2.6V
O.6V
OUTPUT
INPUT REFERENCE
LEVEL
8) Measured with a load equivalent to 1 TIL load and 100pF.
2. v
OUTPUT REFERENCE
LEVEL
9) tcHZ' tOHZ' tWHZ define the time at which the output achieves the open circuit condition and is not referenced to output
voltage levels.
10) For write cycles, the input data is latched at the earlier of RIW or CE1 rising edge (CE2 falling edge). Therefore, the input
data must be valid during the setup time (tosw or tDsd and hold time (tOHW or tOHd.
11) All address inputs are latched at the falling edge of CE1 (rising edge of CE2). Therefore, all the address inputs must be valid
during tAsc and tAHC'
12) The two refresh operations, auto refresh and self refresh, are defined by the RFSH pulse width under the condition
CE1 =V1H or CE2 =V1L.
Auto refresh : RFSH pulse width ~ tFAP (max.)
Self refresh : RFSH pulse width ~ tFAS (min.)
The timing parameter tFRS must be met for proper device operation under the following conditions:
• after self refresh
• if RFSH = ilL" after power-up
13) Thetimings, teE (min.) and tCE (max.) must be met for proper device operation.
VVIL - IH_~
VVll- I H _ = k
VIH_
eE2 VIL -
VIH_
eE2 VIL -
14) The timings, teES (min.) and teEH (min.) must be met when using CE1 and CE2 as shown below.
rn VVIL-IH_~
rn ~:~=~
VIH_
eE2 V1L -
- tas
VIH_
eE2 VIL-
taN
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TC518128BPUBFUBFWUBFTL-70Vl80Vl10V
Static RAM
Data Retention Characteristics (Ta = 0 - 70"C)
SYMBOL
PARAMETER
VOH Data Retention Supply Voltage
IOOF2 Self Refresh Current
tR Recovery Time
I VDH = 3.0V
IVOH = 5.5V
MIN. TYP.
2.7 -
- 15
- 35
5-
MAX.
5.5
25
50
-
UNIT
V
~
ms
Voo
Voo
4.SV
VOH
-_-._-.----_-.-_----.~-
~-----------------~
'I
~.--.-_-.-_-.--.--.-_----
GND
RFSH
VIH
GND
tRFO. I
~
DATA RETENTION MODE
(SELF REFRESH)
Onsmin.
:a O.2V
tR
_I tF~
~
n
-------]
~VDO - O.2V
,.--,
j
~-------
CE2 ~ Voo - O.2V or CE2 :a O.2V
or
- - - - - - - -\l -
~l
GNO
:aO.2V
m m~ Voo - O.2V or
:a O.2V
Notes:
OE, RfIN, AO - A16 = V1H or V1L
IODF1 is applicable when RFSH = V1L (max.), CE1 = V1H (min.), CE2 = V1L (max.).
V'
n ~-------
0-74
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Timing Waveforms
Read Cycle
VIH -
VIL -
VIH
eE2 Vil
Static RAM
TC518128BPUBFUBFWUBFTL-70V/80Vl10V
VIH -
M VIL-----------~~~---+~--------------~+-------~-------------
VIH -~--------~~~------~----------------------~--------~+---~----------
RIW VIL _______--'
toHZ
VOH-
I/01-I/08VOL_--------------~~----+-----------~
DATA·OUT
VIH -
l(nH'VIL _
--------------------~--------------------------------~----~--------
Write Cycle 1 (OE Fixed High)
rn VIH -
eE2
VIH
AO- A16 VIL
m VIH -
VIL -
VIH -
RIW VIL -
ADDRESS
1101-1/08
VIH
VIL
_- ---------------H-----------------<J
DATA·IN
~-------~------~
tFRS
tRFD
VIH-~--~==~~~~~====~-----------------------1~~~~~----
l(nH'VIL_
----------~--------~-----------------~-~:~H~o-r-L------~----~--------
Note: The device can be operated by cycling CE1 (or CE2) only provided that CE2 (or CE1) is connected to V1H (or V1U'
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TC518128BPUBFUBFWUBFTL-70Vl80Vl10V
Write Cycle 2 (OE Clocked)
Static RAM
m
eE2
VIH -
M VIL -:.....------4-4---..J.-+--------:---P-----++-----_--
VIH -
R/W VIL -:.....-------~-4-4--------+--~~-~~~--+~~---++---------------
VIH
VIL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H
-
-
-
-
-
+
-
-
-
+
-
-
-
-
<
J
[
)~A--l'!'-~~~----__:-r__~.
1/01-1108
L OUT VVOOHL- --------------~----~
~VIVLIH --:.....____~~______~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~______~~___
Write Cycle 3 (OE Fixed Low)
VIL -~-------~~----------------------------t+------------
VIH -
R/W VIL -~-----~--~~---------~--~~~----~~---t+----------
rN
VIH
VIL
-----------H------~--+--~[)~-A-:--...zr;..-~---_:_~~
1/01-1/08
L--OUT VOH-"______________~----~
VOL-
VIH -
~VIL -~____~~_____~~_____________==~-----'-------~-------
~:HorL
Note: The device can be operated by cycling CE1 (or CE2) only provided that CE2 (or CE1) is connected to V1H (or V1U'
0-76
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Read Modify Write Cycle
Static RAM
TC518128BPUBFUBFWUBFTl-70Vl80Vl10V
CE2
VIH -
M
V1L -
V1H -
R/VII VIL -
r N ~:~ =--------+-+--+-+_-----+--h----<J,,___~~~~::~------
LV01-V08
OUT VVOOHL- ---------~~-+--~
________________ __ _______~VIVLIH --~______~~========~========~~
~~ ~~
CE Only Refresh
m VIH -
VIL -
CE2
VIH
AO- A8 V1L
VIH -
M
VIL -
VIH -
RIW
VIL -
VOH-
I/Ol-VOS VOL-
~VIV1LH --
=Note: A9 - A 16 V1H or V1L
tFRS
Note: The device can be operated by cycling CE1 (or CE2) only provided that CE2 (or CE1) is connected to V1H (or V1U.
~:HorL
TOSHIBA AMERICA ELECTRONIC COMPONENTS. INC.
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TC518128BFL-10V Datasheet PDF
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tC518128BPUBFUBFWUBFTL-70Vl80Vl10V
Auto Refresh
m VIH-
VIL-
eE2
or
VIH_
Vll-
VIH_
tIT
VIL-
VIH_
eE2
VIL-
VIH_
lfmi
VIL-
Static RAM
1101-1108 VOH_
OPEN
VOL- ----------------------------------
Note: OE, RIW, AD - A16 =V1H or V1L
Self Refresh
rn VIH-
V 1L-
VIH_
eE2
V IL -
or
rn V IH ..:..
VIL-
VIH_
eE2
VIL-
VIH_
1mH
VIL-
VOH_
1/01-1108
- - - - - - - - - - - - - - - - - OPEN
VOL-
Note: DE, RIW, AD - A16 = V1H or V1L
~:HorL
~:HorL
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TC518128BFL-10V Datasheet PDF
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Static RAM
TC518128BPUBFUBFWUBFTL-70Vl80Vl10V
IOOEZ Voo Characteristics
(pA)
Typ.
100
50
o~__________________________________~________________~____________________~
2 4 5 6 (V)
VDD
IOOEZ Temp. Characteristics
(pA)
60
Typ.
Voo= 3V
40
20
________ ________________ ____________________________________ ________________
o~
~
~
~
o 25
Ta
70 ( ·C)
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
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TC518128BFL-10V Datasheet PDF
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TC518128BPUBFUBFWUBFTL-70Vl80VI1 OV
Battery Backup Application Example
Static RAM
Voo
Zo
3.9V
2SA 1015
Oi
10000
*1
±~t·1 ~ S~t.mNicd
X3
VOD
0.1pF
3.6V
1 GNO
+
*2
10pF
- 47pF
*1 : Ceramic condenser
*2: Tantalum condenser
(A large bypass condenser is preferable to absorb noise when the power supply is switched.)
This circuit does not have memory protection. Therefore, rapid turnoff of the power supply must be avoided. Enter the Self
Refresh mode before changing to the battery backup power supply.
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