Analog Devices Semiconductor Electronic Components Datasheet



AD5660

12-/14-/16-Bit nanoDAC


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Data Sheet
Single, 12-/14-/16-Bit nanoDAC with
5 ppm/°C On-Chip Reference in SOT-23
AD5620/AD5640/AD5660
FEATURES
Low power, single nanoDACs
AD5660: 16 bits
AD5640: 14 bits
AD5620: 12 bits
12-bit accuracy guaranteed
On-chip, 1.25 V/2.5 V, 5 ppm/°C reference
Tiny 8-lead SOT-23, MSOP, and LFCSP packages
Power-down to 480 nA @ 5 V, 200 nA @ 3 V
3 V/5 V single power supply
Guaranteed 16-bit monotonic by design
Power-on reset to zero/midscale
3 power-down functions
Serial interface with Schmitt-triggered inputs
Rail-to-rail operation
SYNC interrupt facility
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
PRODUCT HIGHLIGHTS
1. 12-/14-/16-bit nanoDAC—12-bit accuracy guaranteed.
2. On-chip, 1.25 V/2.5 V, 5 ppm/°C reference.
3. Available in 8-lead SOT-23, MSOP, and LFCSP packages.
4. Power-on reset to 0 V or midscale.
5. 10 µs settling time.
Table 1. Related Device
Part No.
Description
AD5662
2.7 V to 5.5 V, 16-bit DAC in SOT-23, LFCSP, and
MSOP, external reference
FUNCTIONAL BLOCK DIAGRAM
VREFOUT GND
VDD
POWER-ON
RESET
1.25/2.5V
REF
AD5620/AD5640/AD5660
VFB
DAC
REGISTER
REF(+)
16-BIT
DAC
OUTPUT
BUFFER
VOUT
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
SYNC SCLK DIN
Figure 1.
GENERAL DESCRIPTION
The AD5620/AD5640/AD5660, members of the nanoDAC™
family of devices, are low power, single, 12-/14-/16-bit, buffered
voltage-out DACs and are guaranteed monotonic by design.
The AD5620/AD5640/AD5660-1 parts include an internal,
1.25 V, 5 ppm/°C reference, giving a full-scale output voltage
range of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include
an internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output
voltage range of 5 V. The reference associated with each part is
available at the VREFOUT pin.
The parts incorporate a power-on reset circuit to ensure that the
DAC output powers up to 0 V (AD5620/AD5640/AD5660-1-2)
or midscale (AD5620-3 and AD5660-3) and remains there until
a valid write takes place. The parts contain a power-down
feature that reduces the current consumption of the device to
480 nA at 5 V and provides software-selectable output loads
while in power-down mode. The power consumption is
2.5 mW at 5 V, reducing to 1 µW in power-down mode.
The AD5620/AD5640/AD5660 on-chip precision output
amplifier allows rail-to-rail output swing to be achieved. For
remote sensing applications, the output amplifier’s inverting
input is available to the user. The AD5620/AD5640/AD5660 use
a versatile 3-wire serial interface that operates at clock rates up
to 30 MHz and is compatible with standard SPI®, QSPI™,
MICROWIRE™, and DSP interface standards.
Rev. G
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved.
Technical Support
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AD5620/AD5640/AD5660
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD5620/AD5640/AD5660-2-3 .................................................. 3
AD5620/AD5640/AD5660-1 ...................................................... 5
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
D/A Section ................................................................................. 17
Resistor String ............................................................................. 17
REVISION HISTORY
8/13—Rev. F to Rev. G
Added LFCSP (Throughout)........................................................... 1
Added Thermal Impedance for LFCSP; Table 5........................... 8
Added Figure 5; Renumbered Sequentially .................................. 9
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 26
12/10—Rev. E to Rev. F
Changes to Ordering Guide .......................................................... 25
7/10—Rev. D to Rev. E
Moved Using the AD5660 as an Isolated, Programmable, 4 mA
to 20 mA Process Controller Section........................................... 22
Moved Power Supply Bypassing and Grounding Section......... 23
Changes to Ordering Guide .......................................................... 25
3/10—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 24
Data Sheet
Internal Reference ...................................................................... 17
Output Amplifier........................................................................ 17
Serial Interface ............................................................................ 17
Input Shift Register .................................................................... 18
SYNC Interrupt .......................................................................... 18
Power-On Reset.......................................................................... 19
Power-Down Modes .................................................................. 19
Microprocessor Interfacing....................................................... 19
Applications Information .............................................................. 21
Using a REF19x as a Power Supply for the
AD5620/AD5640/AD5660 ....................................................... 21
Bipolar Operation Using the AD5660 ..................................... 21
Using the AD5660 as an Isolated, Programmable, 4 mA to
20 mA Process Controller ......................................................... 22
Using the AD5620/AD5640/AD5660 with a Galvanically
Isolated Interface ........................................................................ 22
Power Supply Bypassing and Grounding................................ 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 26
10/09—Rev. B to Rev. C
Changes to Ordering Guide .......................................................... 23
5/06—Rev. A to Rev. B
Updated Formatted ............................................................Universal
Updated Temperature Range ............................................Universal
Changes to Table 2.............................................................................3
Changes to Table 5.............................................................................8
Replaced Figure 17, Figure 18, and Figure 19............................. 12
Changes to Ordering Guides .................................................. 23, 24
9/05—Rev. 0 to Rev. A
Changes to Specifications.................................................................5
Changes to Outline Dimensions .................................................. 23
7/05—Revision 0: Initial Version
Rev. G | Page 2 of 28


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Data Sheet
AD5620/AD5640/AD5660
SPECIFICATIONS
AD5620/AD5640/AD5660-2-3
VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, CREFOUT = 100 nF; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE2
AD5660
Resolution
Relative Accuracy
Differential Nonlinearity
AD5640
Resolution
Relative Accuracy
Differential Nonlinearity
AD5620
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
OUTPUT CHARACTERISTICS3
Output Voltage Range
Output Voltage Settling Time
Slew Rate
Capacitive Load Stability
Output Noise Spectral Density
Output Noise (0.1 Hz to 10 Hz)
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE OUTPUT
Output Voltage
Reference TC3
Output Impedance
A Grade1 B Grade1 C Grade1 Unit
Conditions/Comments
16
±32
±1
14
±8
±0.5
12
±6
±0.25
2
10
±10
−0.15
±1
±1.5
±2
±2.5
−75
0
VDD
8
10
1.5
2
10
80
45
5
0.1
0.5
30
5
2.495
2.505
±10
7.5
16
±16
±1
14
±4
±0.5
12
±1
±0.25
2
10
±10
−0.15
±1
±1.5
±2
±2.5
−75
0
VDD
8
10
1.5
2
10
80
45
5
0.1
0.5
30
5
2.495
2.505
±10
7.5
16
±16
±1
14
±4
±0.5
12
±1
±0.25
2
10
±10
−0.15
±1
±1.5
±2
±2.5
−75
0
VDD
8
10
1.5
2
10
80
45
5
0.1
0.5
30
5
2.495
2.505
±5
±10
7.5
Bits min
LSB max
LSB max
Guaranteed monotonic by design
Bits min
LSB max
LSB max
Guaranteed monotonic by design
Bits min
LSB max
LSB max
mV typ
mV max
mV max
% FSR typ
% FSR max
% FSR max
µV/°C typ
ppm typ
dB typ
Guaranteed monotonic by design
All 0s loaded to DAC register
All 1s loaded to DAC register
Of FSR/°C
DAC code = midscale; VDD = 5 V ± 10%
V min
V max
µs typ
µs max
V/µs typ
nF typ
nF typ
nV/√Hz typ
µV p-p typ
nV-s typ
nV-s typ
Ω typ
mA typ
µs typ
¼ to ¾ scale change settling to ±2 LSB
RL = 2 kΩ; 0 pF < CL < 200 pF
¼ to ¾ scale
RL = ∞
RL = 2 kΩ
DAC code = midscale, 10 kHz
DAC code = midscale
1 LSB change around major carry
VDD = 5 V
Coming out of power-down mode; VDD = 5 V
V min
V max
ppm/°C typ
ppm/°C max
kΩ typ
At ambient
Rev. G | Page 3 of 28


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AD5620/AD5640/AD5660
Data Sheet
Parameter
LOGIC INPUTS3
Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
A Grade1 B Grade1 C Grade1 Unit
±2 ±2 ±2 µA max
0.8 0.8 0.8 V max
2 2 2 V min
3 3 3 pF typ
4.5 4.5 4.5 V min
5.5 5.5 5.5 V max
0.55 0.55 0.55 mA typ
1 1 1 mA max
0.48 0.48 0.48 µA typ
1 1 1 µA max
Conditions/Comments
All digital inputs
VDD = 5 V
VDD = 5 V
All digital inputs at 0 V or VDD
DAC active and excluding load current
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
1 Temperature range is −40°C to +105°C, typical at +25°C.
2 Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 128 to Code 16256); AD5620 (Code 32 to Code 4064). Output
unloaded. Linearity tested with VDD = 5.5 V. If part is operated with a VDD < 5 V, the output is clamped to VDD.
3 Guaranteed by design and characterization; not production tested.
Rev. G | Page 4 of 28


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Data Sheet
AD5620/AD5640/AD5660
AD5620/AD5640/AD5660-1
VDD1 = 2.7 V to 3.3 V, RL = 2 kΩ to GND, CL = 200 pF to GND, CREFOUT = 100 nF; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
STATIC PERFORMANCE3
AD5660
Resolution
Relative Accuracy
Differential Nonlinearity
AD5640
Resolution
Relative Accuracy
Differential Nonlinearity
AD5620
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
OUTPUT CHARACTERISTICS4
Output Voltage Range
Output Voltage Settling Time
Slew Rate
Capacitive Load Stability
Output Noise Spectral Density
Output Noise (0.1 Hz to 10 Hz)
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE OUTPUT
Output Voltage
Reference TC4
Output Impedance
A Grade2 B Grade2 C Grade2 Unit
Conditions/Comments
16
±32
±1
14
±8
±0.5
12
±6
±0.25
2
8
±9
±0.15
±0.85
±0.85
±2
±2.5
−60
0
VDD
8
10
1.5
2
10
80
20
5
0.1
0.5
30
6
1.247
1.253
±10
7.5
16
±16
±1
14
±4
±0.5
12
±1
±0.25
2
8
±9
±0.15
±0.85
±0.85
±2
±2.5
−60
0
VDD
8
10
1.5
2
10
80
20
5
0.1
0.5
30
6
1.247
1.253
±10
7.5
16
±16
±1
14
±4
±0.5
12
±1
±0.25
2
8
±9
±0.15
±0.85
±0.85
±2
±2.5
−60
VDD
8
10
1.5
2
10
80
20
5
0.1
0.5
30
6
1.247
1.253
±5
±15
7.5
Bits min
LSB max
LSB max
Guaranteed monotonic by design
Bits min
LSB max
LSB max
Guaranteed monotonic by design
Bits min
LSB max
LSB max
mV typ
mV max
mV max
% FSR typ
% FSR max
% FSR max
µV/°C typ
ppm typ
dB typ
Guaranteed monotonic by design
All 0s loaded to DAC register
All 1s loaded to DAC register
Of FSR/°C
DAC code = midscale; VDD = 3 V ± 10%
V min
V max
µs typ
µs max
V/µs typ
nF typ
nF typ
nV/√Hz typ
µV p-p typ
nV-s typ
nV-s typ
Ω typ
mA typ
µs typ
¼ to ¾ scale change settling to ±2 LSB
RL = 2 kΩ; 0 pF < CL < 200 pF
¼ to ¾ scale
RL = ∞
RL = 2 kΩ
DAC code = midscale, 10 kHz
DAC code = midscale
1 LSB change around major carry
VDD = 3 V
Coming out of power-down mode; VDD = 3 V
V min
V max
ppm/°C typ
ppm/°C max
kΩ typ
At ambient
Rev. G | Page 5 of 28


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AD5620/AD5640/AD5660
Data Sheet
Parameter
LOGIC INPUTS4
Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 2.7 V to 3.3 V
VDD = 2.7 V to 3.3 V
IDD (All Power-Down Modes)
VDD = 2.7 V to 3.3 V
VDD = 2.7 V to 3.3 V
A Grade2 B Grade2 C Grade2 Unit
±1 ±1 ±1 µA max
0.8 0.8 0.8 V max
2 2 2 V min
3 3 3 pF max
2.7 2.7 2.7 V min
3.3 3.3 3.3 V max
0.55 0.55 0.55 mA typ
0.65 0.65 0.65 mA max
0.2 0.2 0.2 µA typ
0.25 0.25 0.25 µA max
Conditions/Comments
All digital inputs
VDD = 3 V
VDD = 3 V
All digital inputs at 0 V or VDD
DAC active and excluding load current
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
1 Part is functional with VDD up to 5.5 V.
2 Temperature range is −40°C to +105°C, typical at +25°C.
3 Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 128 to Code 16256); AD5620 (Code 32 to Code 4064). Output
unloaded.
4 Guaranteed by design and characterization; not production tested.
Rev. G | Page 6 of 28


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Data Sheet
AD5620/AD5640/AD5660
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
t11
t2
t3
t4
t5
t6
t7
t8
t9
t10
Limit at TMIN, TMAX
VDD = 2.7 V to 3.6 V
VDD = 3.6 V to 5.5 V
50 33
13 13
13 13
13 13
55
4.5 4.5
00
50 33
13 13
00
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
SCLK
SYNC
DIN
t10 t1 t9
t8 t4
t3 t2 t7
MSB
t6
t5
LSB
LSB = DB0
MSB = DB23 FOR AD5660
MSB = DB15 FOR AD5620/AD5640
Figure 2. Serial Write Operation
Rev. G | Page 7 of 28


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AD5620/AD5640/AD5660
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
VOUT to GND
VFB to GND
VREFOUT to GND
Digital Input Voltage to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
SOT-23 Package (4-Layer Board)
θJA Thermal Impedance
MSOP Package (4-Layer Board)
θJA Thermal Impedance
θJC Thermal Impedance
LFCSP Package(4-Layer Board)
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering Peak Temperature
SnPb
Pb-Free
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
119°C/W
141°C/W
44°C/W
103°C/W
44.4°C/W
240°C
260°C
Data Sheet
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. G | Page 8 of 28


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Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5620/AD5640/AD5660
VDD 1 AD5620/ 8 GND
VREFOUT 2 AD5640/ 7 DIN
AD5660
VFB 3 TOP VIEW 6 SCLK
(Not to Scale)
VOUT 4
5 SYNC
Figure 3. SOT-23 Pin Configuration
VDD
VREFOUT
VFB
VOUT
1
2
3
4
AD5620/
AD5640/
AD5660
TOP VIEW
(Not to Scale)
8 GND
7 DIN
6 SCLK
5 SYNC
Figure 4. MSOP Pin Configuration
VDD 1
VREFOUT 2
VFB 3
VOUT 4
AD5620/
AD5640/
AD5660
TOP VIEW
8 GND
7 DIN
6 SCLK
5 SYNC
Figure 5. LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD
Power Supply Input. These parts can operate from 2.7 V to 5.5 V. VDD should be decoupled to GND.
2
VREFOUT
Reference Voltage Output.
3 VFB
Feedback Connection for the Output Amplifier. VFB should be connected to VOUT for normal operation.
4 VOUT
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
5 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When
SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following
clocks. The DAC is updated following the 24th clock cycle for the AD5660 and the 16th clock cycle for
AD5620/AD5640 unless SYNC is taken high before this edge. In this case, the rising edge of SYNC acts as an
interrupt, and the write sequence is ignored by the DAC.
6 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz.
7 DIN
Serial Data Input. The AD5660 has a 24-bit shift register, and the AD5620/AD5640 have a 16-bit shift register.
Data is clocked into the register on the falling edge of the serial clock input.
8 GND
Ground Reference Point for all Circuitry on the Part.
Rev. G | Page 9 of 28


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AD5620/AD5640/AD5660
TYPICAL PERFORMANCE CHARACTERISTICS
10
VDD = 5V
8 VREFOUT = 2.5V
TA = 25°C
6
4
2
0
–2
–4
–6
–8
–10
CODE
Figure 6. INL—AD5660-2/AD5660-3
4
VDD = 5V
3
VREFOUT = 2.5V
TA = 25°C
2
1
0
–1
–2
–3
–4
CODE
Figure 7. INL—AD5640-2/AD5640-3
1.0
VDD = 5V
0.8 VREFOUT = 2.5V
TA = 25°C
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 8. INL—AD5620-2/AD6520-3
Data Sheet
1.0
VDD = 5V
0.8 VREFOUT = 2.5V
TA = 25°C
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
CODE
Figure 9. DNL—AD5660-2/AD5660-3
0.5
VDD = 5V
0.4 VREFOUT = 2.5V
TA = 25°C
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
CODE
Figure 10. DNL—AD5640-2/AD5640-3
0.20
0.15
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 11. DNL—AD5620-2/AD6520-3
Rev. G | Page 10 of 28


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Data Sheet
10
VDD = 3V
8 VREFOUT = 1.25V
TA = 25°C
6
4
2
0
–2
–4
–6
–8
–10
CODE
Figure 12. INL—AD5660-1
4
VDD = 3V
3
VREFOUT = 1.25V
TA = 25°C
2
1
0
–1
–2
–3
–4
CODE
Figure 13. INL—AD5640-1
AD5620/AD5640/AD5660
1.0
VDD = 3V
0.8 VREFOUT = 1.25V
TA = 25°C
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
CODE
Figure 15. DNL—AD5660-1
0.5
VDD = 3V
0.4 VREFOUT = 1.25V
TA = 25°C
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
CODE
Figure 16. DNL—AD5640-1
1.0
VDD = 3V
0.8 VREFOUT = 1.25V
TA = 25°C
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 14. INL—AD5620-1
0.20
0.15
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 17. DNL—AD5620-1
Rev. G | Page 11 of 28


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AD5620/AD5640/AD5660
12
10 VDD = 5V
8
6 MAX INL
4
2
MAX DNL
0
–2 MIN DNL
–4
–6
–8
MIN INL
–10
–12
–40
–20
0
20 40 60 80
TEMPERATURE (°C)
Figure 18. INL Error and DNL Error vs. Temperature
100
Data Sheet
200
180
160
140
120
100
80
60
40
VDD = 3.3V
20
0
IDD (mA)
Figure 21. IDD Histogram
VDD = 5V
TA = 25°C
0.4
VDD = 5V
0.2
0
–0.2
GAIN ERROR
FULL SCALE ERROR
–0.4
–40
–20
0
20 40 60 80 100
TEMPERATURE (°C)
Figure 19. Gain Error and Full-Scale Error vs. Temperature
0.50
DAC LOADED WITH
0.40 FULL-SCALE
SOURCING CURRENT
0.30
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
0.20
0.10
0
VDD = 3V
VREFOUT = 1.25V
–0.10
–0.20
–0.30
–0.40
VDD = 5V
VREFOUT = 2.5V
–0.50
–10 –8 –6 –4 –2 0 2 4 6 8
CURRENT (mA)
Figure 22. Headroom at Rails vs. Source and Sink
10
1.6
VDD = 5V
1.4
1.2
1.0 ZERO CODE ERROR
0.8
0.6
0.4 OFFSET ERROR
0.2
0
–40
–20
0
20 40 60 80 100
TEMPERATURE (°C)
Figure 20. Zero-Code and Offset Error vs. Temperature
6.00
5.00
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
4.00
FULL SCALE
3/4 SCALE
3.00
2.00
1.00
MIDSCALE
1/4 SCALE
0 ZERO SCALE
–1.00
–30 –20 –10 0 10 20 30
CURRENT (mA)
Figure 23. Source and Sink Capability—AD5660-2/AD5660-3
Rev. G | Page 12 of 28


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Data Sheet
4.00
3.00
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
FULL SCALE
2.00
1.00
3/4 SCALE
MIDSCALE
1/4 SCALE
0 ZERO SCALE
–1.00
–30 –20 –10 0 10
CURRENT (mA)
20
Figure 24. Source and Sink Capability—AD5660-1
30
0.7
TA = 25°C
0.6
0.5
VDD = 5V
VDD = 3V
0.4
0.3
0.2
0.1
0
512 10512 20512 30512 40512 50512 60512
CODE
Figure 25. Supply Current vs. Code
AD5620/AD5640/AD5660
VDD = 5V
TA = 25°C
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2k
AND 200pF TO GND
VOUT = 909mV/DIV
1
TIME BASE = 4µs/DIV
Figure 27. Full-Scale Settling Time, 5 V
VDD
1 VREF
2
VOUT
3
CH1 2.00V CH2 2.00V
CH3 100mV
M40.0ms
CH1
Figure 28. Power-On Reset to 0 V—AD5660-2
1400
TA = 25°C
1200
1000
800
VDD = 5V
600
VDD = 3V
400
200
0
0 12 3 4
VLOGIC (V)
Figure 26. Supply Current vs. Logic Input Voltage
5
VDD
1
2
VREF
VOUT
3
CH1 2.00V CH2 2.00V
CH3 200mV
M20.0µs
CH1 1.88V
Figure 29. Power-On Reset to Midscale—AD5660-3
Rev. G | Page 13 of 28


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AD5620/AD5640/AD5660
VDD
1
2 VREF
VOUT
3
CH1 1.20V CH2 1.00V
CH3 100mV
M100µs
CH1 1.87V
Figure 30. Power-On Reset to 0 V—AD5660-1
SCLK
1
VDD = 3V
3
VOUT
CH1 2.00V
CH3 50.0mV
M1.00µs
CH2 520mV
Figure 31. Exiting Power-Down to Midscale
Data Sheet
1.250800
1.250600
1.250400
1.250200
1.250000
1.249800
1.249600
1.249400
1.249200
1.249000
1.248800
1.248600
1.248400
0
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
13nS/SAMPLE NUMBER
1LSB CHANGE AROUND MIDSCALE
(0x7FFF TO 0x8000)
GLITCH IMPULSE = 0.284nV-s
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
Figure 33. Digital-to-Analog Glitch Impulse—AD5660-1
2.500250
2.500200
2.500150
2.500100
2.500050
2.500000
2.499950
2.499900
2.499850
2.499800
2.499750
2.499700
2.499650
2.499600
0
VDD = 5V
TA = 25°C
20nS/SAMPLE NUMBER
DAC LOADED WITH MIDSCALE
DIGITAL FEEDTHROUGH = 0.06nV-s
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
Figure 34. Digital Feedthrough
2.501250
2.501000
2.500750
2.500500
2.500250
2.500000
2.499750
2.499500
2.499250
2.499000
2.498750
2.498500
2.498250
2.498000
0
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
13nS/SAMPLE NUMBER
1LSB CHANGE AROUND MIDSCALE
(0x7FFF TO 0x8000)
GLITCH IMPULSE = 0.497nV-s
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
Figure 32. Digital-to-Analog Glitch Impulse—AD5660-2/AD5660-3
16
TA = 25°C
14
12
VDD = 3V
10
8 VDD = 5V
6
4
012 34567 89
CAPACITANCE (nF)
Figure 35. Settling Time vs. Capacitive Load
10
Rev. G | Page 14 of 28


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Data Sheet
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
DAC LOADED WITH MIDSCALE
1
5s/DIV
Figure 36. 0.1 Hz to 10 Hz Output Noise—AD5660-2/AD5660-3
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
DAC LOADED WITH MIDSCALE
1
4s/DIV
Figure 37. 0.1 Hz to 10 Hz Output Noise—AD5660-1
AD5620/AD5640/AD5660
800
TA = 25°C
700 MIDSCALE LOADED
600
500
400
300
VDD = 5V
200 VREFOUT = 2.5V
100 VDD = 3V
VREFOUT = 1.25V
0
100 1000
10000
100000
FREQUENCY (Hz)
Figure 38. Noise Spectral Density
1000000
Rev. G | Page 15 of 28


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AD5620/AD5640/AD5660
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. Figure 6 through Figure 8 show typical INL vs. code.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. Figure 9 through Figure 11 show typical DNL vs. code.
Zero-Code Error
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5620/AD5640/AD5660, because the output of the DAC
cannot go below 0 V. It is due to a combination of the offset
errors in the DAC and the output amplifier. Zero-code error is
expressed in mV. Figure 20 shows a plot of zero-code error vs.
temperature.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range. Figure 19 shows a plot of full-
scale error vs. temperature.
Gain Error
This is a measurement of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Zero-Code Error Drift
This is a measurement of the change in zero-code error with a
change in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
This is a measurement of the change in gain error with changes
in temperature. It is expressed in (ppm of full-scale range)/°C.
Data Sheet
Offset Error
Offset error is a measurement of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV in the linear region of
the transfer function. Offset error is measured on the AD5660
with Code 512 loaded into the DAC register. It can be negative
or positive.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
the change in VDD for the full-scale output of the DAC. It is
measured in dB. VREF is held at 2.5 V, and VDD is varied by ±10%.
Output Voltage Settling Time
This indicates the amount of time for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change. It
is measured from the 24th falling edge of SCLK.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 32 and Figure 33.
Digital Feedthrough
Digital feedthrough is a measurement of the impulse injected
into the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s or vice versa.
Noise Spectral Density
This is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(voltage per √Hz). It is measured by loading the DAC to
midscale and measuring noise at the output. It is measured
in nV/√Hz. Figure 38 shows a plot of noise spectral density.
Rev. G | Page 16 of 28


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Data Sheet
AD5620/AD5640/AD5660
THEORY OF OPERATION
D/A SECTION
The AD5620/AD5640/AD5660 DACs are fabricated on a CMOS
process. The architecture consists of a string DAC followed by an
output buffer amplifier. The parts include an internal 1.25 V/2.5 V,
5 ppm/°C reference that is internally gained up by 2. Figure 39
shows a block diagram of the DAC architecture.
DAC REGISTER
VDD
REF (+)
RESISTOR
STRING
REF (–)
R
GND
Figure 39. DAC Architecture
R
VFB
VOUT
OUTPUT
AMPLIFIER
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
VOUT
=
2
×
VREFOUT
×

D
2N

where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register.
0 to 4095 for AD5620 (12 bit)
0 to 16383 for AD5640 (14 bit)
0 to 65535 for AD5660 (16 bit)
N is the DAC resolution.
R
R
R TO OUTPUT
AMPLIFIER
R
R
Figure 40. Resistor String
RESISTOR STRING
The resistor string section is shown in Figure 40. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
INTERNAL REFERENCE
The AD5620/AD5640/AD5660-1 parts include an internal,
1.25 V, 5 ppm/°C reference, giving a full-scale output voltage of
2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an
internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output
voltage of 5 V. The reference associated with each part is
available at the VREFOUT pin. A buffer is required if the reference
output is used to drive external loads. It is recommended that a
100 nF capacitor is placed between the reference output and
GND for reference stability.
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. This output
buffer amplifier has a gain of 2 derived from a 50 kΩ resistor
divider network in the feedback path. The inverting input of the
output amplifier is available to the user, allowing for remote
sensing. This VFB pin must be connected to VOUT for normal
operation. It can drive a load of 2 kΩ in parallel with 1000 pF to
GND. Figure 22 shows the source and sink capabilities of the
output amplifier. The slew rate is 1.5 V/µs with a ¼ to ¾ full-
scale settling time of 10 µs.
SERIAL INTERFACE
The AD5620/AD5640/AD5660 have a 3-wire serial interface
(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as most DSPs.
See Figure 2 for a timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low.
Data from the DIN line is clocked into the 16-bit shift register
(AD5620/AD5640) or the 24-bit shift register (AD5660) on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5620/AD5640/AD5660 compatible
with high speed DSPs. On the 16th falling clock edge (AD5620/
AD5640) or the 24th falling clock edge (AD5660), the last data
bit is clocked in and the programmed function is executed, that
is, a change in the DAC register contents and/or a change in the
mode of operation is executed. At this stage, the SYNC line can
be kept low or be brought high. In either case, it must be brought
high for a minimum of 33 ns before the next write sequence so
that a falling edge of SYNC can initiate the next write sequence.
Because the SYNC buffer draws more current when VIN = 2 V
than it does when VIN = 0.8 V, SYNC should be idled low between
write sequences for even lower power operation of the parts. As
is mentioned previously, however, SYNC must be brought high
again just before the next write sequence.
Rev. G | Page 17 of 28


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AD5620/AD5640/AD5660
Data Sheet
INPUT SHIFT REGISTER
AD5620/AD5640
The input shift register is 16 bits wide for the AD5620/AD5640
(see Figure 41 and Figure 42). The first two bits are control bits
that control which mode of operation the part is in (normal
mode or any of the three power-down modes). The next
14/12 bits, respectively, are the data bits. These are transferred
to the DAC register on the 16th falling edge of SCLK.
AD5660
The input shift register is 24 bits wide for the AD5660 (see
Figure 43). The first six bits are don’t care bits. The next two are
control bits that control which mode of operation the part is in
(normal mode or any of the three power-down modes). For a more
complete description of the various modes, see the Power-Down
Modes section. The next 16 bits are the data bits. These are
transferred to the DAC register on the 24th falling edge of SCLK.
DB15 (MSB)
SYNC INTERRUPT
In a normal write sequence for the AD5660, the SYNC line is
kept low for at least 24 falling edges of SCLK, and the DAC is
updated on the 24th falling edge. However, if SYNC is brought
high before the 24th falling edge, this acts as an interrupt to the
write sequence. The shift register is reset, and the write sequence
is seen as invalid. Neither an update of the DAC register contents
nor a change in the operating mode occurs (see Figure 44).
Similarly, in a normal write sequence for the AD5620/AD5640,
the SYNC line is kept low for at least 16 falling edges of SCLK,
and the DAC is updated on the 16th falling edge. However, if
SYNC is brought high before the 16th falling edge, this acts as
an interrupt to the write sequence.
DB0 (LSB)
PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
DB15 (MSB)
DATA BITS
Figure 41. AD5620 Input Register Contents
DB0 (LSB)
PD1 PD0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB23 (MSB)
DATA BITS
Figure 42. AD5640 Input Register Contents
DB0 (LSB)
X X X X X X PD1 PD0 D15 D14 D13 D12 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SCLK
DATA BITS
Figure 43. AD5660 Input Register Contents
SYNC
DIN MSB
LSB
MSB
LSB
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 16TH/24TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16TH/24TH FALLING EDGE
Figure 44. SYNC Interrupt Facility
Rev. G | Page 18 of 28


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Data Sheet
POWER-ON RESET
The AD5620/AD5640/AD5660 family contains a power-on
reset circuit that controls the output voltage during power-up.
The AD5620/AD5640/AD5660-1-2 DAC output powers up to
0 V, and the AD5620/AD5660-3 DAC output powers up to
midscale. The output remains at this level until a valid write
sequence is made to the DAC, which is useful in applications
where it is important to know the state of the DAC output while
it is in the process of powering up.
POWER-DOWN MODES
The AD5620/AD5640/AD5660 have four separate modes of
operation. These modes are software-programmable by setting
two bits in the control register. Table 7 and Table 8 show how
the state of the bits corresponds to the operating mode of the
device.
Table 7. Modes of Operation for the AD5660
DB17
DB16
AD5660 Operating Mode
0 0 Normal operation
Power-down modes:
01
1 kΩ to GND
10
100 kΩ to GND
11
Three-state
Table 8. Modes of Operation for the AD5620/AD5640
DB15
DB14
AD5620/AD5640 Operating Mode
0 0 Normal operation
Power-down modes:
01
1 kΩ to GND
10
100 kΩ to GND
11
Three-state
When both bits are set to 0, the part works normally with its
normal power consumption of 550 µA at 5 V. However, for the
three power-down modes, the supply current falls to 480 nA
at 5 V (200 nA at 3 V). Not only does the supply current fall,
but the output stage is internally switched from the output of
the amplifier to a resistor network of known values. The advan-
tage is that the output impedance of the part is known while the
part is in power-down mode. There are three options: the out-
put is connected internally to GND through a 1 kΩ or a 100 kΩ
resistor, or it is left open-circuited (three-stated). The output
stage is shown in Figure 45.
AD5620/AD5640/AD5660
RESISTOR
STRING DAC
AMPLIFIER
VOUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 45. Output Stage During Power-Down
The bias generator, output amplifier, reference, resistor string,
and other associated linear circuitry are all shut down when
power-down mode is activated. However, the contents of the
DAC register are unaffected when in power-down. The time to
exit power-down is typically 5 µs for VDD = 5 V and VDD = 3 V
(see Figure 31).
MICROPROCESSOR INTERFACING
AD5660-to-Blackfin® ADSP-BF53x Interface
Figure 46 shows a serial interface between the AD5660 and the
Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multi-
processor communications. Using SPORT0 to connect to the
AD5660, the setup for the interface is as follows: DT0PRI drives
the DIN pin of the AD5660, while TSCLK0 drives the SCLK of
the part and SYNC is driven from TFS0.
ADSP-BF53x1
AD56601
TFS0
DTOPRI
TSCLK0
SYNC
DIN
SCLK
1 ADDITIONAL PINS OMITTED FOR CLARITY
Figure 46. AD5660-to-Blackfin ADSP-BF53x Interface
Rev. G | Page 19 of 28


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AD5620/AD5640/AD5660
AD5660-to-68HC11/68L11 Interface
Figure 47 shows a serial interface between the AD5660 and the
68HC11/68L11 microcontroller. SCK of 68HC11/68L11 drives
the SCLK of AD5660, and the MOSI output drives the serial
data line of the DAC. The SYNC signal is derived from a port
line (PC7). The setup conditions for correct operation of this
interface are as follows: The 68HC11/68L11 should be con-
figured so that its CPOL bit is 0, and its CPHA bit is 1. When
data is being transmitted to the DAC, the SYNC line is taken
low (PC7). When the 68HC11/68L11 is configured in this way,
data appearing on the MOSI output is valid on the falling edge
of SCK. Serial data from the 68HC11/68L11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. To load data to the
AD5660, PC7 is left low after the first eight bits are transferred, a
second serial write operation is performed to the DAC, and PC7
is taken high at the end of this procedure.
68HC11/68L111
AD56601
PC7
SCK
MOSI
SYNC
SCLK
DIN
1 ADDITIONAL PINS OMITTED FOR CLARITY
Figure 47. AD5660-to-68HC11/68L11 Interface
AD5660-to-80C51/80L51 Interface
Figure 48 shows a serial interface between the AD5660 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/80L51 drives SCLK of the AD5660,
and RxD drives the serial data line of the part. The SYNC signal
is again derived from a bit-programmable pin on the port. In
this case, Port Line P3.3 is used. When data is to be transmitted
to the AD5660, P3.3 is taken low. The 80C51/80L51 transmit
Data Sheet
data only in 8-bit bytes; therefore, only eight falling clock edges
occur in the transmit cycle. To load data to the DAC, P3.3 is left
low after the first eight bits are transmitted, and a second write
cycle is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
output the serial data LSB first; however, the AD5660 requires
its data with the MSB as the first bit received. The 80C51/80L51
transmit routine should take this into account.
80C51/80L511
AD56601
P3.3
TxD
RxD
SYNC
SCLK
DIN
1 ADDITIONAL PINS OMITTED FOR CLARITY
Figure 48. AD5660-to-80C51/80L51 Interface
AD5660-to-MICROWIRE Interface
Figure 49 shows an interface between the AD5660 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5660 on the rising edge of the SK.
MICROWIRE1
AD56601
CS SYNC
SK SCLK
SO DIN
1 ADDITIONAL PINS OMITTED FOR CLARITY
Figure 49. AD5660-to-MICROWIRE Interface
Rev. G | Page 20 of 28


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Data Sheet
APPLICATIONS INFORMATION
USING A REF19x AS A POWER SUPPLY FOR THE
AD5620/AD5640/AD5660
Because the supply current required by the AD5620/AD5640/
AD5660 is extremely low, an alternative option is to use a REF19x
voltage reference (REF195 for 5 V or REF193 for 3 V) to supply
the required voltage to the part (see Figure 50). This is especially
useful if the power supply is quite noisy or if the system supply
voltages are at some value other than 5 V or 3 V, for example, 15 V.
The REF19x outputs a steady supply voltage for the AD5620/
AD5640/AD5660. If the low dropout REF195 is used, the current
it needs to supply to the AD5660 is 500 µA. This is with no load
on the output of the DAC. When the DAC output is loaded, the
REF195 also must supply the current to the load. The total current
required (with a 5 kΩ load on the DAC output) is
500 µA + (5 V/5 kΩ) = 1.5 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 3 ppm (15 µV) for the 1.5 mA
current drawn from it. This corresponds to a 0.197 LSB error
for the AD5660.
15V
REF195
5V
3-WIRE
SERIAL
INTERFACE
SYNC
SCLK
DIN
AD5660
VOUT = 0V TO 5V
Figure 50. REF195 as the Power Supply to the AD5660
AD5620/AD5640/AD5660
BIPOLAR OPERATION USING THE AD5660
The AD5660 is designed for single-supply operation, but a
bipolar output range is also possible using the circuit in
Figure 51. Figure 51 gives an output voltage range of ±5 V.
Rail-to-rail operation at the amplifier output is achievable
using an AD820 or an OP295 as the output amplifier.
The output voltage for any input code can be calculated as
VO
=
VDD
× 
D
65536
 ×

R1+ R2
R1

VDD
×

R2
R1

where D represents the input code in decimal (0 to 65535).
When VDD = 5 V, R1 = R2 = 10 kΩ,
VO
=

10× D
65536

5
V
This results in an output voltage range of ±5 V, with 0x0000
corresponding to a −5 V output and 0xFFFF corresponding to a
+5 V output.
R2
10k
R1
+5V 10k
10µF
0.1µF
VDD
VFB
VOUT
AD5660
+5V
AD820/
OP295
–5V
±5V
3-WIRE
SERIAL
INTERFACE
Figure 51. Bipolar Operation with the AD5660
Rev. G | Page 21 of 28


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AD5620/AD5640/AD5660
Data Sheet
R2
18.5k
P2
4mA
ADJUST
ADR02
VLOOP
12V TO 36V
SERIAL
LOAD
AD5660
R1 P1
4.7k20mA
ADJUST
AD8627
R6
3.3k
Q1
2N3904
R3
1.5k
D1
R7
100
4–20mA
RL
Figure 52. Programmable 4 mA to 20 mA Process Controller
USING THE AD5660 AS AN ISOLATED,
PROGRAMMABLE, 4 mA TO 20 mA PROCESS
CONTROLLER
In many process-control system applications, 2-wire current
transmitters are used to transmit analog signals through noisy
environments. These current transmitters use a zero-scale signal
current of 4 mA to power the signal conditioning circuitry of
the transmitter. The full-scale output signal in these transmitters
is 20 mA. The converse approach to process control can also be
used, in which a low-power, programmable current source is
used to control remotely located sensors or devices in the loop.
A circuit that performs this function is shown in Figure 52.
Using the AD5660 as the controller, the circuit provides a
programmable output current of 4 to 20 mA, proportional to
the digital code of the DAC. Biasing for the controller is provided
by the ADR02 and requires no external trim for two reasons: first,
the ADR02’s tight initial output voltage tolerance, and second,
the low supply current consumption of both the AD8627 and
the AD5660. The entire circuit, including optocouplers, consumes
less than 3 mA from the total budget of 4 mA. The AD8627
regulates the output current to satisfy the current summation
at the noninverting node of the AD8627.
Without this diode, such transients could cause phase reversal
of the AD8627 and possible latch-up of the controller. The loop
supply voltage compliance of the circuit is limited by the maximum
applied input voltage to the ADR02 and is from 12 V to 40 V.
USING THE AD5620/AD5640/AD5660 WITH A
GALVANICALLY ISOLATED INTERFACE
For process-control applications in industrial environments, it
is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from hazardous
common-mode voltages that might occur in the area where
the DAC is functioning. The iCoupler® provides isolation in
excess of 2.5 kV. The AD5620/AD5640/AD5660 use a 3-wire
serial logic interface; therefore, the ADuM1300 3-channel
digital isolator provides the required isolation (see Figure 53).
The power supply to the part also must be isolated, which is
done by using a transformer. On the DAC side of the trans-
former, a 5 V regulator provides the 5 V supply required for the
AD5620/AD5640/AD5660.
POWER
5V
REGULATOR
10µF 0.1µF
IOUT = 1/R7 (VDAC × R3/R1 + VREF × R3/R2)
For the values shown in Figure 52,
IOUT = 0.2435 µA × D + 4 mA
SCLK
V1A VOA
ADuM1300
SCLK
VDD
AD56x0
where D = 0 ≤ D ≤ 65,535, giving a full-scale output current of
20 mA when the AD5660’s digital code equals 0xFFFF. Offset
trim at 4 mA is provided by P2, and P1 provides the circuit gain
trim at 20 mA. These two trims do not interact because
the noninverting input of the AD8627 is at virtual ground. The
Schottky diode, D1, is required in this circuit to prevent loop
supply power-on transients from pulling the noninverting input
of the AD8627 more than 300 mV below its inverting input.
SDI V1B
DATA
V1C
VOB
SYNC
VOUT
VOC
DIN
GND
Figure 53. AD5620/AD5640/AD5660 with a Galvanically Isolated Interface
Rev. G | Page 22 of 28


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Data Sheet
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5620/
AD5640/AD5660 should have separate analog and digital
sections, each having its own area of the board. If the AD5620/
AD5640/AD5660 are in a system where other devices require
an AGND-to-DGND connection, the connection should be
made at one point only. This ground point should be as close as
possible to the AD5620/AD5640/AD5660.
The power supply to the AD5620/AD5640/AD5660 should be
bypassed with 10 µF and 0.1 µF capacitors. The capacitors
should be as close as physically possible to the device, with the
0.1 µF capacitor ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. It is important that the
0.1 µF capacitor has a low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of
common ceramic types of capacitors. This 0.1 µF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
AD5620/AD5640/AD5660
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other components with
fast switching digital signals should be shielded from other
parts of the board by digital ground. Avoid crossover of digital
and analog signals if possible. When traces cross on opposite
sides of the board, ensure that they run at right angles to each
other to reduce feedthrough effects on the board. The best
board layout technique is the microstrip technique, where the
component side of the board is dedicated to the ground plane
only and the signal traces are placed on the solder side.
However, this is not always possible with a 2-layer board.
Rev. G | Page 23 of 28


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AD5620/AD5640/AD5660
OUTLINE DIMENSIONS
3.00
2.90
2.80
1.70
1.60
1.50
PIN 1
INDICATOR
1.30
1.15
0.90
0.15 MAX
0.05 MIN
8765
1234
3.00
2.80
2.60
1.95
BSC
0.65 BSC
1.45 MAX
0.95 MIN
0.22 MAX
0.08 MIN
0.38 MAX
0.22 MIN
SEATING
PLANE
0.60
BSC
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 54. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
3.20
3.00
2.80
3.20
3.00
2.80
PIN 1
IDENTIFIER
85
14
0.65 BSC
5.15
4.90
4.65
0.95
0.85
0.75
0.15
0.05
COPLANARITY
0.10
1.10 MAX
15° MAX
0.40
0.25
0.23
0.09
0.80
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 55. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Data Sheet
Rev. G | Page 24 of 28


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Data Sheet
AD5620/AD5640/AD5660
PIN 1 INDEX
AREA
0.80
0.75
0.70
SEATING
PLANE
3.10
3.00 SQ
2.90
1.95 REF
0.65 BSC
58
TOP VIEW
0.50
0.40
0.30
41
BOTTOM VIEW
PIN 1 CORNER
C 0.130× 45°
0.05 MAX
0.00 MIN
COPLANARITY
0.35 0.08
0.30 0.203 REF
0.25
COMPLIANT TO JEDEC STANDARDS MO-229-WEEC-2
Figure 56. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-15)
Dimensions shown in millimeters
Rev. G | Page 25 of 28


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AD5620/AD5640/AD5660
ORDERING GUIDE
Model1
AD5620ARJZ-1500RL7
AD5620ARJ-2500RL7
AD5620ARJZ-2500RL7
AD5620ARJ-2REEL7
AD5620ARJZ-2REEL7
AD5620ARMZ-2
AD5620ARMZ-2REEL7
AD5620BCPZ-1500RL7
AD5620BCPZ-1RL7
AD5620BCPZ-2500RL7
AD5620BCPZ-2RL7
AD5620BRJ-1500RL7
AD5620BRJZ-1500RL7
AD5620BRJ-1REEL7
AD5620BRJ-2500RL7
AD5620BRJZ-2500RL7
AD5620BRJ-2REEL7
AD5620BRJZ-2REEL7
AD5620CRM-1
AD5620CRMZ-1
AD5620CRM-1REEL7
AD5620CRMZ-1REEL7
AD5620CRM-2
AD5620CRM-2REEL7
AD5620CRMZ-2
AD5620CRMZ-2REEL7
AD5620CRM-3
AD5620CRMZ-3
AD5620CRMZ-3REEL7
EVAL-AD5620EBZ
AD5640ARJ-2500RL7
AD5640ARJZ-2500RL7
AD5640ARJZ-2REEL7
AD5640BCPZ-1500RL7
AD5640BCPZ-1RL7
AD5640BCPZ-2500RL7
AD5640BCPZ-2RL7
AD5640BRJ-1500RL7
AD5640BRJZ-1500RL7
AD5640BRJ-1REEL7
AD5640BRJZ-1REEL7
AD5640BRJZ-2500RL7
AD5640BRJ-2REEL7
AD5640BRJZ-2REEL7
AD5640CRM-1
AD5640CRM-1REEL7
AD5640CRMZ-1
AD5640CRMZ-1REEL7
AD5640CRM-2
AD5640CRM-2REEL7
AD5640CRMZ-2
AD5640CRMZ-2REEL7
Temperature
Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package
Description
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead MSOP
8-Lead MSOP
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Evaluation Board
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Data Sheet
Package
Option
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RM-8
RM-8
CP-8-15
CP-8-15
CP-8-15
CP-8-15
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
Branding
D6V
D2L
D5D
D2L
D5D
DGY
DGY
DL9
DL9
DLC
DLC
D2H
D87
D2H
D2J
D5C
D2J
D5C
D2M
DGM
D2M
DGM
D2N
D2N
D59
D59
D2P
DGN
DGN
Power-On
Reset to Code
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Midscale
Midscale
Midscale
Accuracy
±6 LSB INL
±6 LSB INL
±6 LSB INL
±6 LSB INL
±6 LSB INL
±6 LSB INL
±6 LSB INL
±6 LSB INL
±6 LSB INL
±6 LSB INL
±6 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
Internal
Reference
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
1.5 V
1.5 V
2.5 V
2.5 V
1.25 V
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
1.25 V
1.25 V
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
RJ-8
RJ-8
RJ-8
CP-8-15
CP-8-15
CP-8-15
CP-8-15
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
D2T
DC6
DC6
DLV
DLV
DLW
DLW
D2Q
DC3
D2Q
DC3
DC0
D2R
DC0
D2U
D2U
DG1
DG1
D2V
D2V
DEW
DEW
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
±8 LSB INL
±8 LSB INL
±8 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
2.5 V
2.5 V
2.5 V
1.25 V
1.25 V
2.5 V
2.5 V
1.25 V
1.25 V
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
1.25 V
1.25 V
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
Rev. G | Page 26 of 28


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Data Sheet
Model1
AD5660ACPZ-1500RL7
AD5660ACPZ-1RL7
AD5660ACPZ-2500RL7
AD5660ACPZ-2RL7
AD5660ACPZ-3500RL7
AD5660ACPZ-3RL7
AD5660ARJ-1500RL7
AD5660ARJZ-1500RL7
AD5660ARJ-1REEL7
AD5660ARJZ-1REEL7
AD5660ARJZ-2500RL7
AD5660ARJ-2REEL7
AD5660ARJZ-2REEL7
AD5660ARJ-3500RL7
AD5660ARJZ-3500RL7
AD5660ARJ-3REEL7
AD5660ARJZ-3REEL7
AD5660BCPZ-1500RL7
AD5660BCPZ-1RL7
AD5660BCPZ-2500RL7
AD5660BCPZ-2RL7
AD5660BCPZ-3500RL7
AD5660BCPZ-3RL7
AD5660BRJ-1500RL7
AD5660BRJZ-1500RL7
AD5660BRJ-1REEL7
AD5660BRJZ-1REEL7
AD5660BRJZ-2500RL7
AD5660BRJZ-2REEL7
AD5660BRJ-3500RL7
AD5660BRJZ-3500RL7
AD5660BRJ-3REEL7
AD5660BRJZ-3REEL7
AD5660CRM-1
AD5660CRM-1REEL7
AD5660CRMZ-1
AD5660CRMZ-1REEL7
AD5660CRM-2
AD5660CRM-2REEL7
AD5660CRMZ-2
AD5660CRMZ-2REEL7
AD5660CRM-3
AD5660CRM-3REEL7
AD5660CRMZ-3
AD5660CRMZ-3REEL7
EVAL-AD5660EBZ
Temperature
Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
1 Z = RoHS Compliant Part.
Package
Description
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Evaluation Board
AD5620/AD5640/AD5660
Package
Option
CP-8-15
CP-8-15
CP-8-15
CP-8-15
CP-8-15
CP-8-15
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
CP-8-15
CP-8-15
CP-8-15
CP-8-15
CP-8-15
CP-8-15
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
Branding
DLM
DLM
DLX
DLX
DLY
DLY
D30
D5G
D30
D5G
D6K
D31
D6K
D32
DAV
D32
DAV
DLZ
DLZ
DM0
DM0
DM1
DM1
D2X
D6C
D2X
D6C
D6L
D6L
D2Z
DAN
D2Z
DAN
D33
D33
DEX
DEX
D34
D34
DEY
DEY
D35
D35
DBY
DBY
Power-On
Reset to Code
Zero
Zero
Zero
Zero
Midscale
Midscale
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Midscale
Midscale
Midscale
Midscale
Zero
Zero
Zero
Zero
Midscale
Midscale
Zero
Zero
Zero
Zero
Zero
Zero
Midscale
Midscale
Midscale
Midscale
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Midscale
Midscale
Midscale
Midscale
Accuracy
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±32 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
Internal
Reference
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
1.25 V
1.25 V
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
1.25 V
1.25 V
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
1.25 V
1.25 V
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
Rev. G | Page 27 of 28


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NOTES
Data Sheet
©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04539-0-8/13(G)
Rev. G | Page 28 of 28




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