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Data Sheet
FEATURES
16-bit resolution AD5545
14-bit resolution AD5555
±1 LSB DNL monotonic
±1 LSB INL
2 mA full-scale current ±20%, with VREF = 10 V
0.5 µs settling time
2Q multiplying reference-input 6.9 MHz BW
Zero or midscale power-up preset
Zero or midscale dynamic reset
3-wire interface
Compact 16-lead TSSOP package
APPLICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
Industrial control PLCs
Programmable attenuator
PRODUCT OVERVIEW
The AD5545/AD5555 are 16-bit/14-bit, current-output, digital-
to-analog converters designed to operate from a 4.5 V to 5.5 V
supply range.
An external reference is needed to establish the full-scale
output-current. An internal feedback resistor (RFB) enhances
the resistance and temperature tracking when combined
with an external op amp to complete the I-to-V conversion.
A serial data interface offers high speed, 3-wire microcontroller
compatible inputs using serial data in (SDI), clock (CLK), and
chip select (CS). Additional LDAC function allows
simultaneous update operation. The internal reset logic allows
power-on preset and dynamic reset at either zero or midscale,
depending on the state of the MSB pin.
The AD5545/AD5555 are packaged in the compact TSSOP-16
package and can be operated from −40°C to +85°C.
Dual, Current-Output,
Serial-Input, 16-/14-Bit DACs
AD5545/AD5555
FUNCTIONAL BLOCK DIAGRAM
VREFA VREFB
16 OR 14
VDD
D0..DX
SDI INPUT
REGISTER R
DAC A
REGISTER R
CS
CLK
EN
DAC A
B
ADDR
DECODE
DGND
INPUT
REGISTER R
DAC B
REGISTER R
POWER-
ON
RESET
RS MSB
LDAC
Figure 1.
DAC A
DAC B
RFBA
IOUTA
AGNDA
RFBB
IOUTB
AGNDB
AD5545/
AD5555
02918-0-001
Rev. I
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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AD5545/AD5555
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Product Overview............................................................................. 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics ............................................................. 3
Timing Diagrams.......................................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Digital-to-Analog Converter ...................................................... 9
Serial Data Interface................................................................... 10
Power-Up Sequence ................................................................... 11
REVISION HISTORY
1/16—Rev. H to Rev. I
Deleted Positive Voltage Output Section and Figure 22;
Renumbered Section ...................................................................... 12
Changes to Ordering Guide .......................................................... 23
4/14—Rev. G to Rev. H
Change to Interface Timing Parameter, Table 1 ........................... 3
4/13—Rev. F to Rev. G
Changes to Product Overview Section.......................................... 1
Changes to Ordering Guide .......................................................... 23
2/13—Rev. E to Rev. F
Change to VDD Pin Description, Table 3 ..................................... 6
Changed ADA4899 to ADA4899-1, Table 12 ............................. 16
Changes to Ordering Guide .......................................................... 23
12/11—Rev. D to Rev. E
Added Figure 13; Renumbered Sequentially ................................ 8
5/11—Rev. C to Rev. D
Added Evaluation Board for the AD5545 Section, System
Demonstration Platform Section, and Operating the Evaluation
Board Section .................................................................................. 17
Added Figure 25 and Figure 26; Renumbered Sequentially ..... 17
Added Evaluation Board Schematics Section, Figure 27 .......... 18
Added Figure 28.............................................................................. 19
Data Sheet
Layout and Power Supply Bypassing ....................................... 11
Grounding ................................................................................... 11
Applications Information .............................................................. 12
Stability ........................................................................................ 12
Bipolar Output............................................................................ 12
Programmable Current Source ................................................ 13
DAC with Programmable Input Reference Range................ 14
Reference Selection .................................................................... 15
Amplifier Selection .................................................................... 15
Evaluation Board for the AD5545................................................ 17
System Demonstration Platform.............................................. 17
Operating the Evaluation Board .............................................. 17
Evaluation Board Schematics ................................................... 18
Evaluation Board Layout........................................................... 21
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
Added Figure 29 ............................................................................. 20
Added Evaluation Board Layout Section, Figure 30, and
Figure 31, ......................................................................................... 21
Added Figure 32 ............................................................................. 22
Changes to Ordering Guide .......................................................... 23
3/11—Rev. B to Rev. C
Change to Equation 4, Bipolar Output Section.......................... 12
4/10—Rev. A to Rev. B
Changes to 2Q Multiplying Reference Input .................................1
Changes to AC Characteristics and Endnote 3 in Table 1 ...........4
Changes to Figure 13 and Figure 15 ...............................................8
Added Reference Selection Section, Amplifier Selection Section,
and Table 10 .................................................................................... 15
Added Table 11 and Table 12 ........................................................ 16
Changes to Ordering Guide .......................................................... 17
9/09—Rev. 0 to Rev. A
Changes to Features Section ............................................................1
Changes to Static Performance, Relative Accuracy, AD5545C
Parameter, Table 1 .............................................................................3
Moved ESD Caution..........................................................................5
Changes to Ordering Guide .......................................................... 16
7/03—Revision 0: Initial Version
Rev. I | Page 2 of 23


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Data Sheet
AD5545/AD5555
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 5 V ± 10%, IOUT = virtual GND, GND = 0 V, VREF = 10 V, TA = full operating temperature range, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE1
Resolution
Relative Accuracy
Differential Nonlinearity
Output Leakage Current
Full-Scale Gain Error
Full-Scale Temperature Coefficient2
REFERENCE INPUT
VREF Range
Input Resistance
Input Capacitance2
ANALOG OUTPUT
Output Current
Output Capacitance2
LOGIC INPUTS AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
INTERFACE TIMING2, 4
Clock Input Frequency
Clock Width High
Clock Width Low
CS to Clock Setup
Clock to CS Hold
Data Setup
Data Hold
LDAC Setup
Hold
LDAC Width
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
Symbol Conditions
N
INL
DNL
IOUT
GFSE
TCVFS
AD5545, 1 LSB = VREF/216 = 153 µV when VREF = 10 V
AD5555, 1 LSB = VREF/214 = 610 µV when VREF = 10 V
AD5545B
AD5555C
AD5545C
Monotonic
Data = 0x0000, TA = 25°C
Data = 0x0000, TA = TA Max
Data = full scale
VREF
RREF
CREF
IOUT Data = full scale
COUT Code dependent
VIL
VIH
IIL
CIL
fCLK
tCH
tCL
tCSS
tCSH
tDS
tDH
tLDS
tLDH
tLDAC
VDD range
IDD
PDISS
PSS
Logic inputs = 0 V
Logic inputs = 0 V
∆VDD = ±5%
Min Typ Max Unit
16
14
±2
±1
±1
±1
10
20
±1 ±4
1
Bits
Bits
LSB
LSB
LSB
LSB
nA
nA
mV
ppm/°C
–12
5
5
+12 V
kΩ3
pF
2 mA
200 pF
0.8 V
2.4 V
10 µA
10 pF
50 MHz
10 ns
10 ns
0 ns
10 ns
5 ns
10 ns
5 ns
10 ns
10 ns
4.5 5.5 V
10 µA
0.055 mW
0.006 %/%
Rev. I | Page 3 of 23


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AD5545/AD5555
Data Sheet
Parameter
AC CHARACTERISTICS
Output Voltage Setting Time
Reference Multiplying BW
DAC Glitch Impulse
Feedthrough Error
Digital Feedthrough
Total Harmonic Distortion
Analog Crosstalk
Output Spot Noise Voltage
Symbol Conditions
tS
BW
Q
VOUT/VREF
Q
THD
CTA
eN
To ±0.1% full scale, data = zero scale to
full scale to zero scale
VREF = 100 mV rms, data = full scale, C1 = 5.6 pF
VREF = 0 V, data = midscale minus 1 to midscale
Data = zero scale, VREF = 100 mV rms,
f = 1 kHz, same channel
CS = logic high and fCLK = 1 MHz
VREF = 5 V p-p, data = full scale, f = 1 kHz to 10 kHz
VREFB = 0 V, measure VOUTB with VREFA = 5 V p-p
sine wave, data = full scale, f = 1 kHz to 10 kHz
f = 1 kHz, BW = 1 Hz
Min Typ Max Unit
0.5
6.9
–2
–81
7
–104
–95
12
µs
MHz
nV-s
dB
nV-s
dB
dB
nV/√Hz
1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP1177 I-to-V converter amplifier. The AD5545 RFB terminal
is tied to the amplifier output. Typical values represent average readings measured at 25°C.
2 These parameters are guaranteed by design and not subject to production testing.
3 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier and the AD8065 for the THD specification.
4 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
TIMING DIAGRAMS
SDI A1 A0 D15 D14 D13 D12 D11 D10
D1 D0
CLK
CS
LDAC
tCSS
tDS tDH
tCH tCL
Figure 2. AD5545 18-Bit Data Word Timing Diagram
INPUT REG LD
tCSH
tLDS
tLDH
tLDAC
02918-0-003
SDI
CLK
CS
LDAC
A1 A0 D13 D12 D11 D10 D09 D08
tCSS
tDS tDH
tCH tCL
Figure 3. AD5555 16-Bit Data Word Timing Diagram
Rev. I | Page 4 of 23
D1 D0
INPUT REG LD
tCSH
tLDS
tLDH
tLDAC
02918-0-004


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Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VDD to GND
VREF to GND
Logic Inputs to GND
V(IOUT) to GND
Input Current to Any Pin except
Supplies
Package Power Dissipation
Thermal Resistance θJA
16-Lead TSSOP
Maximum Junction Temperature
(TJ max)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
RU-16 (Vapor Phase, 60 sec)
RU-16 (Infrared, 15 sec)
Rating
–0.3 V to +8 V
–18 V to +18 V
–0.3 V to +8 V
–0.3 V to VDD + 0.3 V
±50 mA
(TJ max – TA)/θJA
150°C/W
150°C
–40°C to +85°C
–65°C to +150°C
215°C
220°C
AD5545/AD5555
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. I | Page 5 of 23


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AD5545/AD5555
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
RFBA 1
VREFA 2
IOUTA 3
AGNDA 4
AGNDB 5
IOUTB 6
VREFB 7
RFBB 8
AD5545/
AD5555
TOP VIEW
(Not to Scale)
16 CLK
15 LDAC
14 MSB
13 VDD
12 DGND
11 CS
10 RS
9 SDI
02918-0-002
Figure 4. 16-Lead TSSOP
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
1 RFBA
2 VREFA
3 IOUTA
4 AGNDA
5 AGNDB
6 IOUTB
7 VREFB
8 RFBB
9 SDI
10 RS
11 CS
12 DGND
13 VDD
14 MSB
15 LDAC
16 CLK
Description
Establish voltage output for DAC A by connecting this pin to an external amplifier output.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can
be tied to the VDD pin.
DAC A Current Output.
DAC A Analog Ground.
DAC B Analog Ground.
DAC B Current Output.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage.
This pin can be tied to the VDD pin.
Establish voltage output for DAC B by the RFBB pin connecting to an external amplifier output.
Serial Data Input. Input data loads directly into the shift register.
Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or midscale. Register
Data = 0x0000 when MSB = 0. Register Data = 0x8000 for AD5545 and 0x2000 for AD5555 when
MSB = 1.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register
data to the input register when CS/LDAC returns high. This does not affect LDAC operation.
Digital Ground Pin.
Positive Power Supply Input. Specified range of operation 5 V ± 10%.
MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on.
Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can also be tied
permanently to ground or VDD.
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC
registers. Asynchronous active low input. See Table 7 and Table 8 for operation.
Clock Input. Positive edge clocks data into shift register.
Rev. I | Page 6 of 23


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Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE (Decimal)
02918-0-009
Figure 5. AD5545 Integral Nonlinearity Error
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE (Decimal)
02918-0-010
Figure 6. AD5545 Differential Nonlinearity Error
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
2048
4096
6144 8192 10240 12288 14336 16384
CODE (Decimal)
02918-0-011
Figure 7. AD5555 Integral Nonlinearity Error
AD5545/AD5555
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
0248 4096 6144 8192 10240 12288 14336 16384
CODE (Decimal)
02918-0-012
Figure 8. AD5555 Differential Nonlinearity Error
1.5
VREF = 2.5V
TA = 25°C
1.0
0.5
0
–0.5
INL
DNL
–1.0
–1.5
2
GE
4 68
SUPPLY VOLTAGE VDD (V)
Figure 9. Linearity Errors vs. VDD
5
VDD = 5V
TA = 25°C
4
10
02918-0-013
3
2
1
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOGIC INPUT VOLTAGE VIH (V)
02918-0-014
Figure 10. Supply Current vs. Logic Input Voltage
Rev. I | Page 7 of 23


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AD5545/AD5555
3.0
2.5
2.0
0x5555
1.5
0x8000
1.0
0xFFFF
0.5 0x0000
0
10k
100k
1M
10M
100M
CLOCK FREQUENCY (Hz)
02918-0-015
Figure 11. Supply Current vs. Clock Frequency
90
80
70
60
50
40
30
20
10
0
10
VDD = 5V ± 10%
VREF = 10V
100 1k 10k 100k 1M
FREQUENCY (Hz)
02918-0-016
Figure 12. Power Supply Rejection Ration vs. Frequency
20
0
–20
–40
–60
–80
–100
–120
–140
–160
0
5 10 15 20
FREQUENCY (Hz)
Figure 13. AD5545/AD5555 Analog THD
25
02918-0-113
Data Sheet
2
0
–2
–4
–6
–8
–10
–12
–14
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 14. Reference Multiplying Bandwidth
100M
02918-0-117
CS
VOUT
02918-0-018
–3.70
Figure 15. Settling Time
–3.75
–3.80
–3.85
–3.90
–3.95
–4.00
–4.05
–200
–100
0 100 200
TIME (ns)
300
400
02918-0-119
Figure 16. Midscale Transition and Digital Feedthrough
Rev. I | Page 8 of 23


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Data Sheet
THEORY OF OPERATION
The AD5545/AD5555 contain a 16-/14-bit, current-output,
digital-to-analog converter, a serial-input register, and a DAC
register. Both parts require a minimum of a 3-wire serial data
interface with an additional LDAC for dual channel simultaneous
update.
DIGITAL-TO-ANALOG CONVERTER
The DAC architecture uses a current-steering R-2R ladder
design. Figure 17 shows the typical equivalent DAC. The DAC
contains a matching feedback resistor for use with an external
I-to-V converter amplifier. The RFB pin is connected to the
output of the external amplifier. The IOUT terminal is connected
to the inverting input of the external amplifier. These DACs are
designed to operate with either negative or positive reference
voltages. The VDD power pin is used only by the logic to drive
the DAC switches on and off. Note that a matching switch is
used in series with the internal 5 kΩ feedback resistor. If users
attempt to measure the RFB value, power must be applied to VDD
to achieve continuity. The VREF input voltage and the digital data
(D) loaded into the corresponding DAC register, according to
Equation 1 and Equation 2, determine the DAC output voltage.
VOUT = VREF × D /65,536
(1)
VOUT = VREF × D /16,384
(2)
Note that the output full-scale polarity is the opposite of the
VREF polarity for dc reference voltages.
VREF
2R
R
2R
RR
2R R
5k
VDD
RFB
S2 S1
IOUT
GND
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY:
SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED
02918-0-005
Figure 17. Equivalent R-2R DAC Circuit
AD5545/AD5555
These DACs are also designed to accommodate ac reference input
signals. The AD5545/AD5555 accommodate input reference
voltages in the range of –12 V to +12 V. The reference voltage
inputs exhibit a constant nominal input-resistance value of
5 kΩ, ±30%. The DAC output (IOUT) is code dependent, pro-
ducing various output resistances and capacitances. When
choosing an external amplifier, the user should take into
account the variation in impedance generated by the AD5545/
AD5555 on the amplifiers inverting input node. The feedback
resistance in parallel with the DAC ladder resistance dominates
output voltage noise.
2.500V
VIN
VOUT
ADR03
5V
GND
VREFA 2R
R
2R
RR
VDD
RFBA
2R R 5k
+3V
S2 S1 IOUTA
VCC
VOUT
AD8628
AD5545/AD5555
AGNDA
VEE
LOAD
–3V
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY:
SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED
Figure 18. Recommended System Connections
02918-0-006
Rev. I | Page 9 of 23


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AD5545/AD5555
Data Sheet
SERIAL DATA INTERFACE
The AD5545/AD5555 use a minimum 3-wire (CS, SDI, CLK)
serial data interface for single channel update operation. With
Table 7 as an example (AD5545), users can tie LDAC low and
RS high, and then pull CS low for an 18-bit duration. New serial
data is then clocked into the serial-input register in an 18-bit
data-word format with the MSB bit loaded first. Table 8 defines
the truth table for the AD5555. Data is placed on the SDI pin
and clocked into the register on the positive clock edge of CLK.
For the AD5545, only the last 18-bits clocked into the serial
register are interrogated when the CS pin is strobed high,
transferring the serial register data to the DAC register and
updating the output. If the applied microcontroller outputs
serial data in different lengths than the AD5545, such as 8-bit
bytes, three right justified data bytes can be written to the
AD5545. The AD5545 ignores the six MSB and recognizes the
18 LSB as valid data. After loading the serial register, the rising
edge of CS transfers the serial register data to the DAC register
and updates the output; during the CS strobe, the CLK should
not be toggled.
If users want to program each channel separately but update them
simultaneously, program LDAC and RS high initially, then pull
CS low for an 18-bit duration and program DAC A with the
proper address and data bits. CS is then pulled high to latch data
to the DAC A register. At this time, the output is not updated. To
load DAC B data, pull CS low for an 18-bit duration and program
DAC B with the proper address and data, then pull CS high to
latch data to the DAC B register. Finally, pull LDAC low and then
high to update both the DAC A and DAC B outputs
simultaneously.
Table 6 shows that each DAC A and DAC B can be individually
loaded with a new data value. In addition, a common new data
value can be loaded into both DACs simultaneously by setting Bit
A1 = A0 = high. This command enables the parallel combination
of both DACs, with IOUTA and IOUTB tied together, to act as one
DAC with significant improved noise performance.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to digital ground (DGND) and VDD as shown in
Figure 19.
VDD
DIGITAL
INPUTS
5k
DGND
02918-0-007
Figure 19. Equivalent ESD Protection Circuits
Table 4. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
MSB
LSB
Bit Position B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data Word A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 Note that only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D15 to Bit D0) to the
decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5545 shift register are ignored; only the last 18 bits clocked in
are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 5. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
MSB
LSB
Bit Position
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data Word A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 Note that only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D13 to Bit D0) to the
decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5555 shift register are ignored; only the last 16 bits clocked in
are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 6. Address Decode
A1 A0
00
01
10
11
DAC Decoded
None
DAC A
DAC B
DAC A and DAC B
Rev. I | Page 10 of 23


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Data Sheet
AD5545/AD5555
Table 7. AD5545 Control Logic Truth Table1, 2
CS CLK LDAC RS MSB Serial Shift Register Function
HX
H
HX
No effect
LL
H
HX
No effect
L + H
HX
Shift register data advanced one bit
LH
H
HX
No effect
+ L
H
HX
No effect
HX
HX
HX
HX
HX
L
H
+
H
H
HX
HX
HX
L0
LH
No effect
No effect
No effect
No effect
No effect
Input Register Function
Latched
Latched
Latched
Latched
Selected DAC updated
with current SR current
Latched
Latched
Latched
Latched data = 0x0000
Latched data = 0x8000
1 SR = shift register, + = positive logic transition, and X = don’t care.
2 At power-on, both the input register and the DAC register are loaded with all 0s.
Table 8. AD5555 Control Logic Truth Table1, 2
CS CLK LDAC RS MSB Serial Shift Register Function
HX
H
HX
No effect
LL
H
HX
No effect
L + H
LH
H
HX
HX
Shift register data advanced one bit
No effect
+ L
H
HX
No effect
HX
HX
HX
HX
HX
L
H
+
H
H
HX
HX
HX
L0
LH
No effect
No effect
No effect
No effect
No effect
Input Register Function
Latched
Latched
Latched
Latched
Selected DAC updated
with current SR current
Latched
Latched
Latched
Latched data = 0x0000
Latched data = 0x2000
1 SR = shift register, + = positive logic transition, and X = don’t care.
2 At power-on, both the input register and the DAC register are loaded with all 0s.
DAC Register
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Latched
Latched data = 0x0000
Latched data = 0x8000
DAC Register
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Latched
Latched data = 0x0000
Latched data = 0x2000
POWER-UP SEQUENCE
It is recommended to power-up VDD and ground prior to any
reference voltages. The ideal power-up sequence is AGNDx, DGND,
VDD, VREFx, and digital inputs. A noncompliance power-up
sequence can elevate reference current, but the device will
resume normal operation once VDD is powered.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The input leads should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 µF to 0.1 µF disc or
chip ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or
electrolytic capacitors should also be applied at VDD to minimize
any transient disturbance and to filter any low frequency ripple
(see Figure 20). Users should not apply switching regulators for
VDD due to the power supply rejection ratio degradation over
frequency.
AD5545/
AD5555
VDD
C2
+ C1
10µF
0.1µF
VDD
AGNDX
DGND
02918-0-008
Figure 20. Power Supply Bypassing and Grounding Connection
GROUNDING
The DGND and AGNDx pins of the AD5545/AD5555 refer to the
digital and analog ground references. To minimize the digital
ground bounce, the DGND terminal should be joined remotely
at a single point to the analog ground plane (see Figure 20).
Rev. I | Page 11 of 23


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AD5545/AD5555
APPLICATIONS INFORMATION
STABILITY
VDD
U1
VDD
RFB
C1
VREF
VREF
GND
IOUT
AD8628
VO
AD5545/AD5555 U2
02918-0-020
Figure 21. Operational Compensation Capacitor for Gain Peaking
Prevention
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited GBP, and if there
is excessive parasitic capacitance at the inverting node.
An optional compensation capacitor, C1, can be added for
stability as shown in Figure 21. C1 should be found empirically,
but 6 pF is generally more than adequate for the compensation.
Data Sheet
BIPOLAR OUTPUT
The AD5545/AD5555 is inherently a 2-quadrant multiplying
DAC. It can easily be set up for unipolar output operation. The
full-scale output polarity is the inverse of the reference input
voltage.
In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing. This
is easily accomplished by using an additional external amplifier,
U4, configured as a summing amplifier (see Figure 22). In this
circuit, the second amplifier, U4, provides a gain of 2, which
increases the output span magnitude to 5 V. Biasing the external
amplifier with a 2.5 V offset from the reference voltage results in a
full 4-quadrant multiplying circuit. The transfer equation of this
circuit shows that both negative and positive output voltages are
created because the input data (D) is incremented from code zero
(VOUT = −2.5 V) to midscale (VOUT = 0 V) to full scale (VOUT =
+2.5 V).
VOUT = (D/32,768 − 1) × VREF (AD5545)
(3)
VOUT = (D/8192 − 1) × VREF (AD5555)
(4)
For the AD5545, the external resistance tolerance becomes the
dominant error that users should be aware of.
R1 R2
10kΩ±0.01% 10kΩ±0.01%
C2
+5V
ADR03
5V VOUT VIN
GND
U3
U1
VDD RFB
VREF
GND
C1
IOUT
5kΩ±0.01%
R3
U4 +5V
1/2 V+
AD8620
V–
VO
1/2
AD8620
–5V
–2.5 < VO < +2.5
AD5545/AD5555 U2
02918-0-022
Figure 22. Four-Quadrant Multiplying Application Circuit
Rev. I | Page 12 of 23


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Data Sheet
PROGRAMMABLE CURRENT SOURCE
Figure 23 shows a versatile V-to-I conversion circuit using
improved Howland Current Pump. In addition to the precision
current conversion it provides, this circuit enables a bidirec-
tional current flow and high voltage compliance. This circuit
can be used in a 4 mA to 20 mA current transmitter with up to
a 500 Ω of load. In Figure 23, it shows that if the resistor
network is matched, the load current is
(R2 + R3)
IL =
R1
R3
×VREF × D
(5)
R3, in theory, can be made small to achieve the current needed
within the U3 output current driving capability. This circuit is
versatile such that the AD8510 can deliver ±20 mA in both
directions, and the voltage compliance approaches 15 V, which
is mainly limited by the supply voltages of U3. However, users
must pay attention to the compensation. Without C1, it can be
shown that the output impedance becomes
ZO
=
R1R3(R1+ R2)
R1(R2+ R3)R1(R2
+
R3)
(6)
AD5545/AD5555
If the resistors are perfectly matched, ZO is infinite, which is
desirable, and the resistors behave as an ideal current source.
On the other hand, if they are not matched, ZO can be either
positive or negative. The latter can cause oscillation. As a result,
C1 is needed to prevent the oscillation. For critical applications,
C1 could be found empirically but typically falls in the range of
a few picofarads.
VDD
VREF
U1
VDD RFB
VREF
GND
IOUT
AD5545/AD5555
AD8628
U2
R1' R2'
150k15k
C1
10pF
R1
150k
VDD
U3
V+
AD8510
V–
VSS
R3'
50
R3
50
VL
R2
15k
LOAD IL
02918-0-023
Figure 23. Programmable Current Source with Bidirectional
Current Control and High Voltage Compliance Capabilities
Rev. I | Page 13 of 23


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AD5545/AD5555
DAC WITH PROGRAMMABLE INPUT
REFERENCE RANGE
Because high voltage references can be costly, users may
consider using one of the DACs, a digital potentiometer, and a
low voltage reference to form a single-channel DAC with a
programmable input reference range. This approach optimizes
the programmable range as well as facilitates future system
upgrades with just software changes. Figure 24 shows this
implementation. VREFAB is in the feedback network, therefore,
VREF AB
VREF
 1
RWB
RWA
  VREF_AB
DA
2N
RWB
RWA

(7)
where:
VREFAB = reference voltage of VREFA and VREFB
VREF = external reference voltage
DA = DAC A digital code in decimal
N = number of bits of DAC
RWB and RWA are digital potentiometer 128-step programmable
resistances and are given by
RWB
DC
128
RAB
RWA
128 DC
128
RAB
RWB DC
RWA 128 DC
where DC = digital potentiometer digital code in decimal
(0 ≤ DC ≤ 127).
(8)
(9)
(10)
Data Sheet
By putting Equations 7 through 10 together, the following
results:
VREF AB VREF
1
DC
128 DC

1
DA
2N
DC
128 DC
(11)
Table 9 shows a few examples of VREFAB of the 14-bit AD5555.
Table 9. VREFAB vs. DB and DC of the AD5555
DC DA
VREFAB
0X
VREF
32 0
1.33 VREF
32 8192
1.6 VREF
64 0
2 VREF
64 8192
4 VREF
96 0
4 VREF
96 8192
–8 VREF
The output of DAC B is, therefore,
VOB
VREF
AB
DB
2N
(12)
where DB is the DAC B digital code in decimal.
The accuracy of VREFAB is affected by the matching of the input
and feedback resistors and, therefore, a digital potentiometer is
used for U4 because of its inherent resistance matching. The
AD7376 is a 30 V or ±15 V, 128-step digital potentiometer. If
15 V or ±7.5 V is adequate for the application, a 256-step
AD5260 digital potentiometer can be used instead.
+5V
VDD RFBA IOUTA
VREFA U1A
AGNDA
AD5555
RFBB IOUTB
VREFB U1B
AGNDB
C1 +15V
V+
OP4177
A U4 B
V–
AD7376
+15V
W C2
U2A
–15V
2 U3
2.2p
VIN
35
TEMP TRIM 6
VOUT
OP4177
VREF
GND
4
ADR03
U2C
C3
VREF_AB
POT
OP4177
VOB
U2B
02918-0-024
Figure 24. DAC with Programmable Input Reference Range
Rev. I | Page 14 of 23


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Data Sheet
AD5545/AD5555
REFERENCE SELECTION
When selecting a reference for use with the AD55xx series
of current output DACs, pay attention to the output voltage,
temperature coefficient specification of the reference. Choosing
a precision reference with a low output temperature coefficient
minimizes error sources. Table 10 lists some of the references
available from Analog Devices, Inc., that are suitable for use
with this range of current output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code-dependent output resistance of the DAC,
the input offset voltage of an op amp is multiplied by the variable
gain of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed upon the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, can cause the DAC to be
nonmonotonic.
The input bias current of an op amp also generates an offset at
the voltage output because of the bias current flowing in the
feedback resistor, RFB.
Common-mode rejection of the op amp is important in voltage-
switching circuits because it produces a code-dependent error
at the voltage output of the circuit.
Provided that the DAC switches are driven from true wideband
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage-switching
DAC circuit is determined largely by the output op amp. To obtain
minimum settling time in this configuration, minimize capacitance
at the VREF node (the voltage output node in this application) of
the DAC. This is done by using low input capacitance buffer
amplifiers and careful board design.
Analog Devices offers a wide range of amplifiers for both precision
dc and ac applications, as listed in Table 11 and Table 12.
Table 10. Suitable Analog Devices Precision References
Maximum Temperature
Part No. Output Voltage (V) Initial Tolerance (%) Drift (ppm/°C)
ADR01 10
0.05 3
ADR01 10
0.05 9
ADR02 5.0 0.06 3
ADR02 5.0 0.06 9
ADR03 2.5
0.1
3
ADR03 2.5
0.1
9
ADR06 3.0
0.1
3
ADR06 3.0
0.1
9
ADR420 2.048
0.05
3
ADR421 2.50
0.04
3
ADR423 3.00
0.04
3
ADR425 5.00
0.04
3
ADR431 2.500
0.04
3
ADR435 5.000
0.04
3
ADR391 2.5 0.16 9
ADR395 5.0 0.10 9
ISS (mA)
1
1
1
1
1
1
1
1
0.5
0.5
0.5
0.5
0.8
0.8
0.12
0.12
Output Noise (µV p-p)
20
20
10
10
6
6
10
10
1.75
1.75
2
3.4
3.5
8
5
8
Package(s)
SOIC-8
TSOT-5, SC70-5
SOIC-8
TSOT-5, SC70-5
SOIC-8
TSOT-5, SC70-5
SOIC-8
TSOT-5, SC70-5
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, MSOP-8
TSOT-5
TSOT-5
Rev. I | Page 15 of 23


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AD5545/AD5555
Data Sheet
Table 11. Suitable Analog Devices Precision Op Amps
Part No.
VOS Maximum IB Maximum
Supply Voltage (V) (µV)
(nA)
OP97
±2 to ±20
25
0.1
OP1177
±2.5 to ±15
60
2
AD8675
±5 to ±18
75
2
AD8671
±5 to ±15
75
12
ADA4004-1 ±5 to ±15
125
90
AD8603
1.8 to 5
50
0.001
AD8607
1.8 to 5
50
0.001
AD8605
2.7 to 5
65
0.001
AD8615
2.7 to 5
65
0.001
AD8616
2.7 to 5
65
0.001
0.1 Hz to 10 Hz
Noise (µV p-p)
0.5
0.4
0.1
0.077
0.1
2.3
2.3
2.3
2.4
2.4
Supply Current (µA)
600
500
2300
3000
2000
40
40
1000
2000
2000
Package(s)
SOIC-8, PDIP-8
MSOP-8, SOIC-8
MSOP-8, SOIC-8
MSOP-8, SOIC-8
SOIC-8, SOT-23-5
TSOT-5
MSOP-8, SOIC-8
WLCSP-5, SOT-23-5
TSOT-5
MSOP-8, SOIC-8
Table 12. Suitable Analog Devices High Speed Op Amps
Part No.
Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/µs)
AD8065
5 to 24
145
180
AD8066
5 to 24
145
180
AD8021
5 to 24
490
120
AD8038
3 to 12
350
425
ADA4899-1 5 to 12
600
310
AD8057
3 to 12
325
1000
AD8058
3 to 12
325
850
AD8061
2.7 to 8
320
650
AD8062
2.7 to 8
320
650
AD9631
±3 to ±6
320
1300
VOS (Max) (µV)
1500
1500
1000
3000
35
5000
5000
6000
6000
10,000
IB (Max) (nA)
0.006
0.006
10,500
750
100
500
500
350
350
7000
Package(s)
SOIC-8, SOT-23-5
SOIC-8, MSOP-8
SOIC-8, MSOP-8
SOIC-8, SC70-5
LFCSP-8, SOIC-8
SOT-23-5, SOIC-8
SOIC-8, MSOP-8
SOT-23-5, SOIC-8
SOIC-8, MSOP-8
SOIC-8, PDIP-8
Rev. I | Page 16 of 23


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Data Sheet
EVALUATION BOARD FOR THE AD5545
The EVAL-AD5545SDZ is used in conjunction with an SDP1Z
system demonstration platform board available from Analog
Devices, which is purchased separately from the evaluation
board. The USB-to-SPI communication to the AD5545 is
completed using this Blackfin®-based demonstration board.
SYSTEM DEMONSTRATION PLATFORM
The system demonstration platform (SDP) is a hardware and
software evaluation tool for use in conjunction with product
evaluation boards. The SDP board is based on the Blackfin
ADSP-BF527 processor with USB connectivity to the PC
through a USB 2.0 high speed port. For more information about
this device, see the system demonstration platform web page.
OPERATING THE EVALUATION BOARD
The evaluation board requires ±12 V and +5 V supplies.
The +12 V VDD and −12 V VSS are used to power the output
amplifier, and the +5 V is used to power the DAC (DVDD).
AD5545/AD5555
Figure 26. Evaluation Board Software—AD5545 Dual DAC
Figure 25. Evaluation Board Software – Device Selection Window
Rev. I | Page 17 of 23


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AD5545/AD5555
EVALUATION BOARD SCHEMATICS
Data Sheet
Figure 27. EVAL-AD5545SDZ Schematic Part A
Rev. I | Page 18 of 23


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Data Sheet
AD5545/AD5555
Figure 28. EVAL-AD5545SDZ Schematic Part B
Rev. I | Page 19 of 23


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AD5545/AD5555
Data Sheet
Figure 29. EVAL-AD5545SDZ Schematic Part B
Rev. I | Page 20 of 23


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Data Sheet
EVALUATION BOARD LAYOUT
AD5545/AD5555
Figure 30. Silkscreen
Figure 31. Component Side
Rev. I | Page 21 of 23


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AD5545/AD5555
Data Sheet
Figure 32. Solder Side
Rev. I | Page 22 of 23


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Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16 9
4.50
4.40
4.30
1
6.40
BSC
8
PIN 1
0.15
0.05
1.20
MAX
0.20
0.09
0.65
BSC
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 33. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
AD5545/AD5555
ORDERING GUIDE
Model1, 2
AD5545BRUZ
AD5545BRUZ-REEL7
AD5545CRUZ
AD5545CRUZ-REEL7
AD5555CRU
AD5555CRUZ
AD5555CRUZ-REEL7
EV-AD5544/45SDZ
INL
LSB
±2
±2
±1
±1
±1
±1
±1
DNL Resolution Temperature
LSB (Bits)
Range
±1 16
−40°C to +85°C
±1 16
−40°C to +85°C
±1 16
−40°C to +85°C
±1 16
−40°C to +85°C
±1 14
−40°C to +85°C
±1 14
−40°C to +85°C
±1 14
−40°C to +85°C
Evaluation Board
Package
Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
1 The AD5545/AD5555 contain 3131 transistors. The die size measures 71 mil. × 96 mil., 6816 sq. mil.
2 Z = RoHS Compliant Part.
Package
Option
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
Ordering
Qty
96
1000
96
1000
96
96
1000
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registered trademarks are the property of their respective owners.
D02918-0-1/16(I)
Rev. I | Page 23 of 23





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