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Data Sheet
FEATURES
256-position
End-to-end resistance: 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact SOT-23-8 (2.9 mm × 3 mm) package
SPI-compatible interface
Power-on preset to midscale
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 45 ppm/°C
Low power, IDD = 8 μA
Wide operating temperature: –40°C to +125°C
Evaluation board available
APPLICATIONS
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Gain control and offset adjustment
GENERAL DESCRIPTION
The AD5160 provides a compact 2.9 mm × 3 mm packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function as
mechanical potentiometers1 or variable resistors but with
enhanced resolution, solid-state reliability, and superior low
temperature coefficient performance.
256-Position SPI-Compatible
Digital Potentiometer
AD5160
FUNCTIONAL BLOCK DIAGRAM
VDD
CS
SDI
CLK
SPI INTERFACE
A
W
WIPER
REGISTER
B
GND
Figure 1.
PIN CONFIGURATION
W1
8A
VDD 2
GND 3
CLK 4
AD5160
TOP VIEW
(Not to Scale)
7B
6 CS
5 SDI
Figure 2.
The wiper settings are controllable through an SPI-compatible
digital interface. The resistance between the wiper and either
end point of the fixed resistor varies linearly with respect to the
digital code transferred into the RDAC latch.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 μA allows for usage in portable battery-operated
applications.
1 The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


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AD5160* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
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Evaluation Kits
• AD5160 Evaluation Board
Documentation
Application Notes
• AN-686: Implementing an I2C® Reset
Data Sheet
• AD5160: 256-Position SPI-Compatible Digital
Potentiometer Data Sheet
User Guides
• UG-623: Evaluation Board for the AD5160 Digital
Potentiometer
Software and Systems Requirements
• AD5160 - No-OS Driver for Microchip Microcontroller
Platforms
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Platforms
• Digital Potentiometer Linux Driver
• AD5160 Pmod Xilinx FPGA Reference Design
Reference Materials
Technical Articles
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Design Resources
• AD5160 Material Declaration
• PCN-PDN Information
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AD5160
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Pin Configuration............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 kΩ Version.................................. 3
10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 4
Timing Characteristics—All Versions ....................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
REVISION HISTORY
11/14—Rev. B to Rev. C
Changes to Ordering Guide .......................................................... 16
5/09—Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 16
1/09—Rev. 0 to Rev. A
Deleted Shutdown Supply Current Parameter and
Endnote 7, Table 1 ............................................................................ 3
Changes to Resistor Noise Voltage Density Parameter,
Table 1 ................................................................................................ 3
Deleted Shutdown Supply Current Parameter and
Endnote 7, Table 2 ............................................................................ 4
Changes to Resistor Noise Voltage Density Parameter,
Table 2 ................................................................................................ 4
Added Endnote to Table 3 ............................................................... 5
Changes to Table 4............................................................................ 6
Changes to the Rheostat Operation Section ............................... 14
Deleted Terminal Voltage Operating Range Section and
Figure 41, Renumbered Figures Sequentially ............................. 13
Changes to Figure 40 and Figure 41............................................. 15
Changes to Ordering Guide .......................................................... 16
5/03—Revision 0: Initial Version
Data Sheet
Typical Performance Characteristics ..............................................8
Test Circuits..................................................................................... 12
SPI Interface .................................................................................... 13
Theory of Operation ...................................................................... 14
Programming the Variable Resistor......................................... 14
Programming the Potentiometer Divider............................... 15
SPI-Compatible 3-Wire Serial Bus........................................... 15
ESD Protection ........................................................................... 15
Power-Up Sequence ................................................................... 15
Layout and Power Supply Bypassing ....................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
Rev. C | Page 2 of 16


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Data Sheet
AD5160
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
VDD = 5 V ± 10%, or 3 V ± 10%; VA = +VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS
Rheostat Mode
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
Potentiometer Divider Mode
Resolution
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
Capacitance A, Capacitance B6
Capacitance W6
Common-Mode Leakage
DIGITAL INPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation7
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage Density
Symbol Conditions
Min Typ1 Max Unit
R-DNL
R-INL
∆RAB
∆RAB/∆T
RW
N
DNL
INL
∆VW/∆T
VWFSE
VWZSE
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
VAB = VDD, wiper = no connect
Specifications apply to all VRs
Code = 0x80
Code = 0xFF
Code = 0x00
−1.5 ±0.1 +1.5
−4 ±0.75 +4
−20 +20
45
50 120
LSB
LSB
%
ppm/°C
8 Bits
−1.5 ±0.1 +1.5 LSB
−1.5 ±0.6 +1.5 LSB
15 ppm/°C
−6 −2.5 0
LSB
0 +2 +6 LSB
VA, VB, VW
CA,B
CW
ICM
f = 1 MHz, measured to GND, code = 0x80
f = 1 MHz, measured to GND, code = 0x80
VA = VB = VDD/2
GND
45
60
1
VDD V
pF
pF
nA
VIH
VIL
VIH VDD = 3 V
VIL VDD = 3 V
IIL VIN = 0 V or 5 V
CIL
2.4
2.1
5
V
0.8 V
V
0.6 V
±1 µA
pF
VDD RANGE
IDD
PDISS
PSS
VIH = 5 V or VIL = 0 V
VIH = 5 V or VIL = 0 V, VDD = 5 V
∆VDD = +5 V ± 10%, code = midscale
2.7 5.5 V
3 8 µA
0.2 mW
±0.02 ±0.05 %/%
BW_5K
THDW
tS
eN_WB
RAB = 5 kΩ, code = 0x80
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = 5 V, VB = 0 V, ±1 LSB error band
RWB = 2.5 kΩ
1.2 MHz
0.05 %
1 µs
6 nV/√Hz
1 Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). VA = VDD and VB =
0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
Rev. C | Page 3 of 16


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AD5160
Data Sheet
10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS
Rheostat Mode
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
Potentiometer Divider Mode
Resolution
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature
Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
Capacitance A, Capacitance B6
Capacitance W6
Common-Mode Leakage
DIGITAL INPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation7
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
Resistor Noise Voltage Density
Symbol Conditions
Min Typ1
Max Unit
R-DNL
R-INL
∆RAB
∆RAB/∆T
RW
N
DNL
INL
∆VW/∆T
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
VAB = VDD,
Wiper = no connect
VDD = 5 V
Specifications apply to all VRs
Code = 0x80
VWFSE
VWZSE
Code = 0xFF
Code = 0x00
−1 ±0.1
−2 ±0.25
−15
45
50
−1 ±0.1
−1 ±0.3
15
−3 −1
01
+1 LSB
+2 LSB
+15 %
ppm/°C
120 Ω
8 Bits
+1 LSB
+1 LSB
ppm/°C
0 LSB
3 LSB
VA,B,W
CA,B
CW
ICM
f = 1 MHz, measured to GND, code =
0x80
f = 1 MHz, measured to GND, code =
0x80
VA = VB = VDD/2
GND
45
60
1
VDD V
pF
pF
nA
VIH
VIL
VIH VDD = 3 V
VIL VDD = 3 V
IIL VIN = 0 V or 5 V
CIL
2.4
2.1
5
V
0.8 V
V
0.6 V
±1 µA
pF
VDD RANGE
IDD
PDISS
PSS
VIH = 5 V or VIL = 0 V
VIH = 5 V or VIL = 0 V, VDD = 5 V
∆VDD = +5 V ± 10%, code = midscale
2.7
3
±0.02
5.5
8
0.2
±0.05
V
µA
mW
%/%
BW
THDW
tS
eN_WB
RAB = 10 kΩ/50 kΩ/100 kΩ, Code = 0x80
VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB =
10 kΩ
VA = 5 V, VB = 0 V,
±1 LSB error band
RWB = 5 kΩ
600/100/40
0.05
2
9
kHz
%
µs
nV/√Hz
1 Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). VA = VDD and VB =
0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
Rev. C | Page 4 of 16


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Data Sheet
AD5160
TIMING CHARACTERISTICS—ALL VERSIONS
VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter
SPI INTERFACE TIMING CHARACTERISTICS1, 2
Clock Frequency
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS Setup Time
CS High Pulse Width
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
Symbol
fCLK
tCH, tCL
tDS
tDH
tCSS
tCSW
tCSH0
tCSH1
Conditions
Specifications apply to all parts
Clock level high or low
Min
20
5
5
15
40
0
0
Typ1 Max
25
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
1 See the timing diagram, Figure 38, for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a
voltage level of 1.5 V.
2 Guaranteed by design and not subject to production test.
Rev. C | Page 5 of 16


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AD5160
ABSOLUTE MAXIMUM RATINGS
TA = +25°C, unless otherwise noted.
Table 4.
Parameter
VDD to GND
VA, VB, VW to GND
Maximum Current IMAX1
IWB, IWA Pulsed
IWB, IWA Continuous
5 kΩ, 10 kΩ
50 kΩ
100 kΩ
Digital Inputs and Output Voltage to GND
Temperature
Operating Temperature Range
Maximum Junction Temperature (TJMAX)
Storage Temperature
Thermal Resistance (SOT-23 Package)2
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering (Pb-Free)
Peak Temperature
Time at Peak Temperature
Rating
−0.3 V to +7 V
VDD
±20 mA
4.7 mA
0.95 mA
0.48 mA
0 V to +7 V
−40°C to +125°C
150°C
−65°C to +150°C
206ºC/W
91°C/W
260°C
10 sec to 40 sec
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and applied
voltage across any two of the A, B, and W terminals at a given resistance.
2 Package power dissipation = (TJMAX − TA)/θJA.
Data Sheet
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. C | Page 6 of 16


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Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
W1
8A
VDD 2
GND 3
CLK 4
AD5160
TOP VIEW
(Not to Scale)
7B
6 CS
5 SDI
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin Mnemonic
Description
1W
W Terminal.
2 VDD
Positive Power Supply.
3 GND
Digital Ground.
4 CLK
Serial Clock Input. Positive edge triggered.
5 SDI
Serial Data Input.
6 CS
Chip Select Input, Active Low. When CS returns high, data loads into the DAC register.
7B
B Terminal.
8A
A Terminal.
AD5160
Rev. C | Page 7 of 16


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AD5160
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8 5V
3V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
32 64 96 128 160 192 224
CODE (Decimal)
Figure 4. R-INL vs. Code vs. Supply Voltages
256
1.0
0.8
5V
0.6 3V
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0 32 64 96 128 160 192 224
CODE (Decimal)
Figure 5. R-DNL vs. Code vs. Supply Voltages
256
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
_40°C
+25°C
+85°C
+125°C
32 64 96 128 160 192 224 256
CODE (Decimal)
Figure 6. INL vs. Code, VDD = 5 V
Data Sheet
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
–40°C
+25°C
+85°C
+125°C
32 64 96 128 160 192 224 256
CODE (Decimal)
Figure 7. DNL vs. Code, VDD = 5 V
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
5V
3V
32 64 96 128 160 192
CODE (Decimal)
Figure 8. INL vs. Code vs. Supply Voltages
224
256
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
5V
3V
–0.6
–0.8
–1.0
0
32 64 96 128 160 192 224
CODE (Decimal)
Figure 9. DNL vs. Code vs. Supply Voltages
256
Rev. C | Page 8 of 16


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Data Sheet
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
–40°C
+25°C
+85°C
+125°C
32 64 96 128 160 192 224 256
CODE (Decimal)
Figure 10. R-INL vs. Code, VDD = 5 V
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
_40°C
+25°C
+85°C
+125°C
32 64 96 128 160 192 224 256
CODE (Decimal)
Figure 11. R-DNL vs. Code, VDD = 5 V
2.5
2.0
1.5
VDD = 2.7V
1.0
VDD = 5.5V
0.5
0
–40 0 40 80
TEMPERATURE (°C)
Figure 12. Full-Scale Error vs. Temperature
120
AD5160
2.5
2.0
VDD = 5.5V
1.5
VDD = 2.7V
1.0
0.5
0
–40 0 40 80
TEMPERATURE (°C)
Figure 13. Zero-Scale Error vs. Temperature
120
10
VDD = 5.5V
1
VDD = 2.7V
0.1
–40
0 40 80
TEMPERATURE (°C)
Figure 14. Supply Current vs. Temperature
120
70
60
50
40
30
20 VDD= 5V
10
0
–40 0 40 80 120
TEMPERATURE (°C)
Figure 15. Shutdown Current vs. Temperature
Rev. C | Page 9 of 16


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AD5160
200
150
100
50
0
–50
0
32 64 96 128 160 192 224 256
CODE (Decimal)
Figure 16. Rheostat Mode Tempco ∆RWB/∆T vs. Code
160
140
120
100
80
60
40
20
0
–20
0
32 64 96 128 160 192 224 256
CODE (Decimal)
Figure 17. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
REF LEVEL
0.000dB
0
–6
–12
–18
–24
–30
–36
–42
/DIV
6.000dB
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
MARKER 1 000 000.000Hz
MAG (A/R) –8.918dB
–48
–54
–60
1k
START 1 000.000Hz
10k
100k
1M
STOP 1 000 000.000Hz
Figure 18. Gain vs. Frequency vs. Code, RAB = 5 kΩ
Data Sheet
REF LEVEL
0.000dB
0
–6
–12
–18
–24
–30
–36
–42
/DIV
6.000dB
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
MARKER 510 634.725Hz
MAG (A/R) –9.049dB
–48
–54
–60
1k
START 1 000.000Hz
10k
100k
1M
STOP 1 000 000.000Hz
Figure 19. Gain vs. Frequency vs. Code, RAB = 10 kΩ
REF LEVEL
0.000dB
0
–6
–12
–18
–24
–30
–36
–42
–48
/DIV
6.000dB
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
–54
–60
1k
START 1 000.000Hz
10k
MARKER 100 885.289Hz
MAG (A/R) –9.014dB
100k
1M
STOP 1 000 000.000Hz
Figure 20. Gain vs. Frequency vs. Code, RAB = 50 kΩ
REF LEVEL
0.000dB
0
–6
–12
–18
–24
–30
–36
–42
–48
/DIV
6.000dB
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
MARKER 54 089.173Hz
MAG (A/R) –9.052dB
–54
–60
1k 10k
START 1 000.000Hz
100k
1M
STOP 1 000 000.000Hz
Figure 21. Gain vs. Frequency vs. Code, RAB = 100 kΩ
Rev. C | Page 10 of 16


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Data Sheet
REF LEVEL
–5.000dB
–5.5
–6.0
–6.5
–7.0
/DIV
0.500dB
5k– 1.026 MHz
10k– 511 MHz
50k– 101 MHz
100k– 54 MHz
–7.5
–8.0
–8.5
–9.0
–9.5
R = 100k
R = 50k
R = 10k
R = 5k
–10.0
–10.5
10k
100k
START 1 000.000Hz
1M 10M
STOP 1 000 000.000Hz
Figure 22. –3 dB Bandwidth @ Code = 0x80
60
CODE = 0x80, VA= VDD, VB = 0V
40
PSRR @ VDD = 3V DC ± 10% p-p AC
20
PSRR @ VDD = 5V DC ± 10% p-p AC
0
100
1k 10k 100k
FREQUENCY (Hz)
Figure 23. PSRR vs. Frequency
900
VDD = 5V
800
700
600
500
400
300
200
100
0
10k
CODE = 0x55
CODE = 0xFF
100k
1M
FREQUENCY (Hz)
Figure 24. IDD vs. Frequency
1M
10M
AD5160
1 VW
CLK
2
Ch 1 200mV BW Ch 2 5.00 V BW M 100ns A CH2 3.00 V
Figure 25. Digital Feedthrough
VA = 5V
VB = 0V
1 VW
CS
2
Ch 1 100mV BW Ch 2 5.00 V BW M 200ns A CH1 152mV
Figure 26. Midscale Glitch, Code 0x80 to Code 0x7F
VA = 5V
VB = 0V
1 VW
CS
2
Ch 1 5.00V BW Ch 2 5.00 V BW M 200ns A CH1 3.00 V
Figure 27. Large Signal Settling Time, Code 0xFF to Code 0x00
Rev. C | Page 11 of 16


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AD5160
Data Sheet
TEST CIRCUITS
Figure 28 to Figure 36 illustrate the test circuits that define the test conditions used in the product specification tables.
5V
DUT
A
V+ W
B
V+ = VDD
1LSB = V+/2N
VMS
OFFSET
GND
OP279
VIN
W
A DUT
OFFSET
BIAS
B
VOUT
Figure 28. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 33. Test Circuit for Noninverting Gain
NO CONNECT
DUT
A
W
B
IW
VMS
Figure 29. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
VMS2
DUT
A
W
B
IW = VDD / RNOMINAL
VW
VMS1 RW = [VMS1 – VMS2]/ IW
Figure 30. Test Circuit for Wiper Resistance
VA
VDD A
V+ W
B
( )V+= VDD 10%
PSRR (dB) = 20 LOG
V MS
V DD
PSS (%/%) = VMS%
V DD%
VMS
Figure 31. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
A
VIN DUT
OFFSET
GND
2.5V
B
W
+15V
AD8610
–15V
VOUT
Figure 34. Test Circuit for Gain vs. Frequency
DUT
W
B
RSW =
0.1V
ISW
CODE = 0x00
ISW 0.1V
VSS TO VDD
Figure 35. Test Circuit for Incremental On Resistance
NC
VDD DUT
VSS GND
A
W
B
ICM
VCM
NC NC = NO CONNECT
Figure 36. Test Circuit for Common-Mode Leakage Current
OFFSET
GND
A DUT B
VIN W
OFFSET
BIAS
5V
OP279
VOUT
Figure 32. Test Circuit for Inverting Gain
Rev. C | Page 12 of 16


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Data Sheet
SPI INTERFACE
Table 6. Serial Data-Word Format
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
27 20
AD5160
1
SDI
0
1
CLK
0
1
CS
0
1
VOUT
0
D7 D6 D5 D4 D3 D2 D1 D0
RDAC REGISTER LOAD
Figure 37. SPI Interface Timing Diagram
(VA = 5 V, VB = 0 V, VW = VOUT)
SDI
(DATA IN)
1
0
Dx
CLK
CS
1
0
tCSHO
tCSS
1
0
tCH
VDD
VOUT
0
Dx
tDS
tCL
tCH tCS1
tCSH1
tCSW
tS
Figure 38. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
±1LSB
Rev. C | Page 13 of 16


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AD5160
THEORY OF OPERATION
The AD5160 is a 256-position digitally controlled variable
resistor (VR) device.
An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The
final two or three digits of the model number as listed in the
Ordering Guide section determine the nominal resistance value,
for example, in model AD5160BRJZ10, the 10 represents 10 kΩ;
and in AD5160BRJZ50, the 50 represents 50 kΩ.
The nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal, plus the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of the 256
possible settings.
Assuming a 10 kΩ part is used, the first connection of the wiper
starts at the B terminal for Data 0x00. Because there is a 60 Ω
wiper contact resistance, such connection yields a minimum of
60 Ω resistance between Terminal W and Terminal B.
The second connection is the first tap point, which corresponds
to 99 Ω (RWB = RAB/256 + RW = 39 Ω + 60 Ω) for Data 0x01.
The third connection is the next tap point, representing 138 Ω
(2 × 39 Ω + 60 Ω) for Data 0x02, and so on. Each LSB data
value increase moves the wiper up the resistor ladder until the
last tap point is reached at 9961 Ω (RAB − 1 LSB + RW). Figure 39
shows a simplified diagram of the equivalent RDAC circuit
where the last resistor string is not accessed; therefore, there is
1 LSB less of the nominal resistance at full scale in addition to
the wiper resistance.
A
RS
D7
D6
D5
RS
D4
D3
D2 RS
D1
D0
W
RDAC
LATCH
AND
RS
DECODER
B
Figure 39. Equivalent RDAC Circuit
Data Sheet
The general equation determining the digitally programmed
output resistance between W and B is
RWB
(D )
D
256
R AB
RW
(1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if RAB = 10 kΩ and the A terminal is open
circuited, the following output resistance RWB is set for the
indicated RDAC latch codes.
Table 7. Codes and Corresponding RWB Resistance
D (Dec.) RWB (Ω) Output State
255
9961
Full Scale (RAB − 1 LSB + RW)
128
5060
Midscale
1 99 1 LSB
0 60 Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition, a finite wiper resistance of
60 Ω is present. Take care to limit the current flow between W
and B in this state to a maximum pulse current of no more than
20 mA. Otherwise, degradation or possible destruction of the
internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the Wiper W and Terminal A also produces a
digitally controlled complementary resistance (RWA). When
these terminals are used, the B terminal can be opened. Setting
the resistance value for RWA starts at a maximum value of
resistance and decreases as the data loaded in the latch increases
in value. The general equation for this operation is
RWA (D)
256 D
256
R AB
RW
(2)
For RAB = 10 kΩ and the B terminal is open circuited, the
following output resistance RWA is set for the indicated RDAC
latch codes.
Table 8. Codes and Corresponding RWA Resistance
D (Dec.)
RWA (Ω)
Output State
255 99 Full Scale
128
5060
Midscale
1
9961
1 LSB
0
10,060
Zero Scale
Typical device-to-device matching is process lot dependent and
may vary by up to ±30%. Because the resistance element is
processed in thin film technology, the change in RAB with
temperature has a very low 45 ppm/°C temperature coefficient.
Rev. C | Page 14 of 16


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Data Sheet
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across Terminal A and Terminal B divided by
the 256 positions of the potentiometer divider. The general
equation defining the output voltage at VW with respect to
ground for any valid input voltage applied to Terminal A and
Terminal B is
VW
(D )
D
256
VA
256 D
256
VB
(3)
For a more accurate calculation, which includes the effect of
wiper resistance, VW can be found as
VW
(D )
RWB (D
256
)
V
A
RWA (D
256
)
V
B
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors (RWA and RWB) and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
SPI-COMPATIBLE 3-WIRE SERIAL BUS
The AD5160 contains a 3-wire SPI-compatible digital interface
(SDI, CS, and CLK). The 8-bit serial word must be loaded MSB
first. The format of the word is shown in Table 6.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is low, the clock
loads data into the serial register on each positive clock edge
(see Figure 37).
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5160 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Extra MSB bits are ignored.
AD5160
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures are shown in Figure 40 and
Figure 41. This applies to SDI, CLK, and CS, which are the
digital input pins.
340
LOGIC
GND
Figure 40. ESD Protection of Digital Pins
A,B,W
GND
Figure 41. ESD Protection of Resistor Terminals
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at the A, B, and W terminals, it is important to power VDD/GND
before applying any voltage to the A, B, and W terminals;
otherwise, the diode forward biases such that VDD is powered
unintentionally and may affect the rest of the user’s circuit. The
ideal power-up sequence is in the following order: GND, VDD,
digital inputs, and then VA/B/W. The relative order of powering
VA, VB, VW, and the digital inputs is not important as long as
they are powered after VDD/GND.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. Keep the leads to the inputs as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Bypass supply
leads to the device with disc or chip ceramic capacitors of
0.01 μF to 0.1 μF. To minimize any transient disturbance and
low frequency ripple, apply low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors at the supplies (see Figure 42). To
minimize the ground bounce, join the digital ground remotely
to the analog ground at a single point.
VDD
C3 + C1
10F 0.1F
VDD
AD5160
GND
Figure 42. Power Supply Bypassing
Rev. C | Page 15 of 16


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AD5160
Data Sheet
OUTLINE DIMENSIONS
3.00
2.90
2.80
1.70
1.60
1.50
PIN 1
INDICATOR
1.30
1.15
0.90
8765
1234
3.00
2.80
2.60
1.95
BSC
0.65 BSC
1.45 MAX
0.95 MIN
0.22 MAX
0.08 MIN
0.15 MAX
0.05 MIN
0.38 MAX
0.22 MIN
SEATING
PLANE
0.60
BSC
0.60
0.45
0.30
ORDERING GUIDE
Model1, 2, 3
AD5160BRJZ5-R2
AD5160BRJZ5-RL7
AD5160BRJZ10-R2
AD5160BRJZ10-RL7
AD5160BRJZ50-R2
AD5160BRJZ50-RL7
AD5160BRJZ100-R2
AD5160BRJZ100-RL7
EVAL-AD5160DBZ
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 43. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
RAB (Ω)
5k
5k
10 k
10 k
50 k
50 k
100 k
100 k
Temperature
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
Evaluation Board
Package Option
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
RJ-8
Branding
D6Q
D6Q
D09
D09
D8J
D8J
D0B
D0B
1 The AD5160 contains 2532 transistors. Die size: 30.7 mil × 76.8 mil = 2358 sq. mil.
2 Z = RoHS Compliant Part.
3 The EVAL-AD5160DBZ board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
©2003–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03434-0-11/14(C)
Rev. C | Page 16 of 16





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