Fairchild Semiconductor Electronic Components Datasheet



FPF3040

18V-Rated Dual Input Single Output Power-Source-Selector Switch


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November 2014
FPF3040
IntelliMAX18 V-Rated Dual Input Single Output
Power-Source-Selector Switch
Features
Dual-Input, Single-Output Load Switch
Input Supply Operating Range:
- 4~10.5 V at VIN
- 4~6.5 V at VBUS
Typical RON:
- 95 mΩ at VIN=5 V
- 70 mΩ at VBUS=5 V
Bi-Directional Switch for VIN and VBUS
Slew Rate Controlled:
- 50 µs at VIN for < 4.7 µF COUT
- 90 µs at VBUS for < 4.7 µF COUT
Maximum ISW: 2 A Per Channel
Break-Before-Make Transition
Under-Voltage Lockout (UVLO)
Over-Voltage Lockout (OVLO)
Thermal Shutdown
Logic CMOS IO Meets JESD76 Standard for GPIO
Interface and Related Power Supply Requirements
ESD Protected:
- Human Body Model: >3 kV
- Charged Device Model: >1.5 kV
- IEC 61000-4-2 Air Discharge: >15 kV
- IEC61000-4-2 Contact Discharge: >8 kV
Description
The FPF3040 is a 18 V-rated Dual-Input Single-Output
(DISO) load switch consisting of two channels of slew-
rate-controlled, low-on-resistance, N-channel MOSFET
switches with protection features. The slew-rate-
controlled turn-on characteristic prevents inrush current
and the resulting excessive voltage droop on the input
power rails. The input voltage range operates from
4 V to 6.5 V at VBUS and from 4 V to 10.5 V at VIN to
align with the needs of low-voltage portable device
power rails.
VIN and VBUS have the over-voltage protection
functionality of typical 12 V and 7.5 V, respectively, to
avoid unwanted damage to system.
VIN and VBUS bi-directional switching allows reverse
current from VOUT to VIN or VBUS for On-The-Go, (OTG)
Mode. The switching is controlled by logic input EN and
VIN_SEL is capable of interfacing directly with low-voltage
control signal General-Purpose Input / Output (GPIO).
FPF3040 is available in 1.8 mm x 2.0 mm Wafer-Level
Chip-Scale Package (WLCSP), 16-bump, 0.4 mm pitch.
Applications
Input Power Selection Block Supporting USB and
Wireless Charging
Smartphone / Tablet PC
Ordering Information
Part Number
FPF3040UCX
Top
Mark
QY
Channel
DISO
Typical RON per
Channel at 5VIN
95 for VIN
70 for VBUS
Rise Time (tR)
Package
50 µs for VIN 1.8 mm x 2.0 mm Wafer-Level Chip-Scale
90 µs for VBUS Package (WLCSP), 16-Bump, 0.4 mm Pitch
© 2012 Fairchild Semiconductor Corporation
FPF3040 • Rev. 2.4.3
www.fairchildsemi.com


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Application Diagram
CIN1
CIN2
OFF ON
VIN VOUT
VIN VOUT
VIN VOUT
VOUT
VBUS
VBUS
VBUS FPF3040
EN DF_IN
VIN_ SEL
Other_VIN_ AVA
GNDGND
COUT
VI/O
Figure 1. Typical Application
EN FPF3040 VOUT
1.8V GPIO
Q1
R1
20 kΩ
R2
30 kΩ
Charger
5V charging voltage at VOUT creates 3V at EN when
Q1 gate is LOW (OFF)
Note:
Q1 gate should be HIGH (ON) when not in OTG mode.
Figure 2. Example Circuit for OTG Operation with Low-Voltage GPIO
© 2012 Fairchild Semiconductor Corporation
FPF3040 Rev. 2.4.3
2
www.fairchildsemi.com


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Block Diagram
VIN
VIN
VIN
VBUS
VBUS
VBUS
FPF3040
OVP
HV Power Device
SW1
C1
HV Power Device
SW2
C2
VMAX
VCC
VCC
EN
VIN_SEL
GND
GND
Startup
Reference Voltage
Reference Current
Thermal Protection
VGATE
VREF
TSD
Gate Driver
&
Logic Control
C1
C2
VOUT
VOUT
VOUT
VOUT
Other_VIN_AVA
DF_IN
Figure 3. Functional Block Diagram
© 2012 Fairchild Semiconductor Corporation
FPF3040 Rev. 2.4.3
3
www.fairchildsemi.com


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Pin Configuration
Figure 4. Pin Assignment (Top View)
Figure 5. Pin Assignment (Bottom View)
Pin Description
Pin #
A1, B1, C1
A4, B4, C4
A2, A3, B3, C3
C2
D4
D3
B2
D1, D2
Name
VBUS
VIN
VOUT
EN
VIN_SEL
DF_IN
Other_VIN_AVA
GND
Input / Output
Description
Input / Output
Input / Output
Input / Output
VBUS at USB: Power input / output.
bi-directional switch when VIN_SEL = LOW.
VIN Supply Input: Power input / output.
bi-directional switch when VIN_SEL = HIGH.
Switch Output: Power input / output.
Input
Enable: Active HIGH.
EN voltage ≥ 2.5 V can power internal circuit when VIN and VBUS
are absent.
1 pull-down resistor is included.
Input / Output
Input
Supply Selector & Status: Input power source selection input
and status output. This signal is ignored during EN=LOW.
Selector input during EN=HIGH:
HIGH = switch VIN to VOUT / LOW = switch VBUS to VOUT.
Status output during EN=LOW:
HIGH = VIN is used for VOUT / LOW = VBUS is used for VOUT.
Default Supply Selector during EN=LOW: Input.
Floating = VBUS connects to VOUT.
LOW means VIN connects to VOUT.
This signal is ignored during EN=HIGH. 1 µA pull-up current
source is included.
Output
Other Supply Input Status: Open-drain output.
HI-Z = both VIN and VBUS are valid.
LOW = the other power source is not valid.
Ground
© 2012 Fairchild Semiconductor Corporation
FPF3040 Rev. 2.4.3
4
www.fairchildsemi.com


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Table 1.
Truth Table
EN VIN>UVLO VBUS>UVLO VIN_SEL
HIGH
X
X LOW
HIGH
LOW
X
YES
X HIGH
NO HIGH
DF_IN
X
X
X
Other_VIN_AVA
HI-Z if VIN & VBUS >UVLO
LOW if VIN or VBUS
<UVLO
HI-Z if VIN & VBUS >UVLO
LOW if VIN or VBUS
<UVLO
LOW
LOW
NO
YES
LOW
X
LOW
LOW YES
YES LOW Floating
HIGH
LOW YES
YES HIGH LOW
HIGH
LOW
NO
NO X
Notes:
1. Internal pull-down at EN.
2. 1 µA pull-up current source at DF_IN.
X
LOW
VOUT
VBUS
VIN
VIN
VBUS
VBUS
VIN
Floating
Comment
VOUT is selected by
VIN_SEL
Bi-directional channel
Automatic selection to
valid input
VIN_SEL is output.
VOUT is selected by
DF_IN
VIN_SEL is output.
OFF
Absolute Maximum Ratings
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameters
Min. Max. Unit
VPIN
VIN, VBUS to GND
VOUT to GND(3)
Continuous
Pulsed, 100 ms Maximum Non-Repetitive
EN, DF_IN, VIN_SEL, Other_VIN_AVA to GND
ISW Maximum Continuous Switch Current per Channel
-1.4
18
-2.0
-0.3 16.0
-0.3 6.0
2
V
A
tPD Total Power Dissipation at TA=25°C
2.25 W
TJ Operating Junction Temperature
-40 +150 °C
TSTG Storage Junction Temperature
JA Thermal Resistance, Junction-to-Ambient (1in. Square Pad of 2 oz. Copper)
-65 +150 °C
55(4) °C/W
Human Body Model, JESD22-A114
3
ESD
Electrostatic Discharge
Capability
Charged Device Model, JESD22-C101
IEC61000-4-2 Air Discharge (VIN, VBUS to GND)
System Level(5) Contact Discharge (VIN, VBUS to GND)
1.5
15
8
kV
Notes:
3. If external voltage of more than 10.5 V is applied to VOUT, the slew rate should be less than 1 V/ms from 10.5 V.
4. Measured using 2S2P JEDEC standard PCB.
5. System level ESD can be guaranteed by design.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VPIN
TA
VIN
VBUS
Ambient Operating Temperature
Parameters
Min.
4.0
4.0
-40
Max.
10.5
6.5
+85
Unit
V
°C
© 2012 Fairchild Semiconductor Corporation
FPF3040 Rev. 2.4.3
5
www.fairchildsemi.com


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Electrical Characteristics
VIN=4 to 10.5 V, VBUS=4 to 6.5 V, TA=-40 to 85°C unless otherwise noted. Typical values are at VIN=VBUS=5 V,
EN=HIGH and TA=25°C unless otherwise noted.
Symbol
Parameters
Condition
Min. Typ. Max. Unit
Basic Operation
VIN
VBUS
Input Voltage
4.0
4.0
IQ Quiescent Current
IOUT=0 mA, EN=HIGH,
VIN or VBUS=5 V
IOUT=0 mA, EN=5 V,
VIN and VBUS=GND
VIN=8 V, IOUT=200 mA, TA=25°C
On Resistance for VIN
RON
VIN=5 V, IOUT=200 mA, TA=25°C
VIN=5 V, IOUT=200 mA,
TA=25°C to 85°C(6)
VBUS=6 V, IOUT=200 mA, TA=25°C
On Resistance for VBUS
VBUS=5 V, IOUT=200 mA, TA=25°C
VBUS=5 V, IOUT=200 mA,
TA=25°C to 85°C(6)
VIH Input Logic High Voltage
VIN=4 V~10.5 V, VBUS=4 V ~ 6.5 V
1.15
VIL Input Logic Low Voltage
VEN(OTG) EN Voltage in OTG Mode(6)
VIN=4 V~10.5 V, VBUS=4 V ~ 6.5 V
VIN & VBUS=Float or VIN & VBUS <VUVLO
2.5
REN_PD Pull-Down Resistance at EN
Protection
707
VUVLO
Under-Voltage Lockout
Threshold
VIN or VBUS Rising
VIN or VBUS Falling
3.05
2.55
VUVHYS
Under-Voltage Lockout
Hysteresis
VIN Rising Threshold
10.85
VIN Falling Threshold
VOVLO Over-Voltage Lockout Threshold
VBUS Rising Threshold
6.52
VBUS Falling Threshold
VOVHYS
Over-Voltage Lockout
Hysteresis
VIN
VBUS
TSDN Thermal Shutdown Threshold
TSDNHYS Thermal Shutdown Hysteresis
Reverse Current Blocking
IRCB VIN or VBUS Current During RCB VOUT=8 V, VIN or VBUS=GND
Dynamic Characteristics
tR
tF
tTRAN
tSD
VOUT Rise Time, VBUS(6,7)
VOUT Rise Time, VIN(6,7)
VOUT Fall Time(6,7)
Transition Delay(6,7)
Selection Delay(6,7)
VIN=VBUS=5 V, RL=150 Ω, CL=4.7 μF,
TA=25°C
50
Notes:
6. This parameter is guaranteed by characterization and/or design; not production tested.
7. tSD/tTRAN/tR/tF are defined in Figure 6.
© 2012 Fairchild Semiconductor Corporation
FPF3040 Rev. 2.4.3
6
10.5 V
6.5 V
55 120 μA
33 70 μA
95
95 150 mΩ
200
70
70 100 mΩ
140
0.52
1000 1360
V
V
V
kΩ
3.50 4.00
3.00 3.55
0.5
12.00
11.5
7.50
7
0.5
0.5
150
20
13.45
8.32
V
V
V
V
V
V
V
V
V
°C
°C
30 μA
90 μs
50
1.4 ms
100 ms
50 μs
www.fairchildsemi.com


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Timing Diagram
Figure 6. Transition Delay (VIN=VBUS=5 V)
© 2012 Fairchild Semiconductor Corporation
FPF3040 Rev. 2.4.3
7
www.fairchildsemi.com


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Typical Characteristics
Figure 7. VIN Quiescent Current (Iq) vs. Temperature Figure 8. VBUS Quiescent Current (Iq) vs. Temperature
Figure 9. VIN Quiescent Current vs. Supply Voltage Figure 10.VBUS Quiescent Current vs. Supply Voltage
Figure 11.VIN On Resistance (mΩ) vs. Temperature Figure 12.VBUS On Resistance (mΩ) vs. Temperature
Figure 13.VIN On Resistance (mΩ) vs. Supply Voltage Figure 14.VBUS On Resistance (mΩ) vs. Supply Voltage
© 2012 Fairchild Semiconductor Corporation
FPF3040 Rev. 2.4.3
8
www.fairchildsemi.com


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Typical Characteristics (Continued)
Figure 15.VIN_SEL Input Logic High & Low Voltage
vs. Temperature
Figure 16.EN Input Logic High & Low Voltage
vs. Temperature
Figure 17.DF_IN Logic High & Low Voltage
vs. Temperature
Figure 18.VIN_VULVO vs. Temperature
Figure 19.VBUS_VULVO vs. Temperature
Figure 20.VIN_VOVLO vs. Temperature
Figure 21.VBUS_VOVLO vs. Temperature
Figure 22.VOUT tR vs. Temperature
© 2012 Fairchild Semiconductor Corporation
FPF3040 Rev. 2.4.3
9
www.fairchildsemi.com


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Typical Characteristics (Continued)
Figure 23.VOUT tF vs. Temperature
Figure 24.tTRAN vs. Temperature
Figure 25.Power Source Transition (VIN=VBUS=5 V,
EN=HIGH, VIN_SEL=LOWHIGHLOW,
COUT=4.7 µF, RL=150 )
Figure 26.VIN On Response (VIN=GND5 V,
VBUS=EN=GND, COUT=4.7 µF, RL=150 )
Figure 27.VBUS On Response (VBUS=GND5 V,
VIN=EN=GND, COUT=4.7 µF, RL=150 Ω)
Figure 28.Off Response (VIN=VBUS=5 V, EN=HIGH,
VIN_SEL=LOHIGH or HIGHLOW, COUT=4.7 µF,
RL=150 Ω)
Figure 29.VIN Over-Voltage Protection Response
(VIN=5 V15 V, VBUS=5 V, EN=VIN_SEL=HIGH,
COUT=4.7 µF, RL=150 )
Figure 30.VBUS Over-Voltage Protection Response
(VBUS=5 V15 V, VIN=5 V, EN=HIGH,
VIN_SEL=LOW, COUT=4.7 µF, RL=150 )
© 2012 Fairchild Semiconductor Corporation
FPF3040 Rev. 2.4.3
10
www.fairchildsemi.com


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Operation and Application Information
The FPF3040 is a 18 V, 2 A-rated, Dual-Input Single-
Output (DISO) load switch with slew-rate-controlled,
low-on-resistance, based-on-N-channel MOSFET. The
input operating range is from 4 V to 6.5 V at VBUS and
from 4 V to 10.5 V at VIN. The internal circuitry is
powered from the highest voltage source among VIN,
VBUS, and VEN.
Input Power Source Selection
Input power source can be selected by VIN_SEL and
DF_IN, respectively, depending on EN state. When EN
is HIGH, the input source is selected by VIN_SEL
regardless of DF_IN. If VIN_SEL is LOW, VBUS is selected.
If VIN_SEL is HIGH, VIN is selected.
Table 2. Input Power Selection by VIN_SEL
EN VIN>UVLO VBUS>UVLO VIN_SEL DF_IN VOUT
HIGH
X
X
LOW
X VBUS
HIGH
X
X HIGH X VIN
When EN is LOW, the input source is selected by
DF_IN and the number of valid input sources. If only
one input source is valid, or more than UVLO, the
source is selected automatically, regardless of DF_IN,
to make a charging path in case the battery is depleted.
If both VBUS and VIN have valid input sources, the input
source is selected by DF_IN. If DF_IN is LOW, VIN is
selected. If DF_IN is HIGH or floating, VBUS is selected.
DF_IN is biased HIGH with an internal 1 µA pull-up
current source.
Table 3. Input Power Selection by DF_IN
EN VIN>UVLO VBUS>UVLO VIN_SEL DF_IN VOUT
LOW
YES
NO
HIGH X
VIN
LOW
NO
YES
LOW X VBUS
LOW
LOW
LOW
YES
YES
NO
YES
YES
NO
LOW
HIGH
X
Floating VBUS
LOW
VIN
X Floating
VIN_SEL can be the status output to indicate which input
power source is used during EN is LOW. If VIN is used,
VIN_SEL shows high. If VBUS is used, VIN_SEL shows LOW.
The voltage level of HIGH signal is 5.3 V if any one of
VIN, VBUS or EN is higher than 5.3 V. The signal is
highest voltage among VIN, VBUS, and VEN if none of
them is higher than 5.3 V.
EN Voltage for Control Logic Power
Supply
Internal control logic is powered from the highest
voltage among VIN, VBUS, and VEN. If valid VIN or VBUS
higher than UVLO is applied, ON/OFF control by EN
should be accomplished with VIH/VIL. If EN powers the
internal control block without valid VIN and VBUS, more
than 2.5 V is required on the EN pin to operate properly.
Over-Voltage Protection (OVP)
FPF3040 has over-voltage protection at both VIN and
VBUS. If VIN or VBUS is higher than 12 V or 7.5 V,
respectively, the power switch is off until input voltage is
lower than the over-voltage trip level by hysteresis
voltage of 0.5 V.
Reverse Power Supply for OTG
FPF3040 has a bi-directional switch so reverse power is
allowed for On-The-Go (OTG) operation. Even if both VIN
and VBUS are not available, reverse power can be also
supported if internal control circuitry is powered by EN.
Reverse-Current Blocking
FPF3040 supports reverse-current blocking during EN
LOW and an unselected channel.
Thermal Shutdown
During FPF3040 thermal shutdown, the power switch is
turned off if junction temperature reaches over 150°C to
avoid damage.
Wireless Charging System
FPF3040 can be used for an input power selector
supporting Travel Adaptor (TA) and Wireless Charging
(WC) with a single-input-based battery charger or Power
Management IC (PMIC), including a charging block as
shown in Figure 31. The system can recognize an input
power source change between 5 V TA and 5 V WC
without detection circuitry because FPF3040 has a
100 ms transition delay. OTG Mode can be supported
without an additional power path, such as a MOSFET.
Travel Adaptor
(5V)
Wireless Charging
(5V)
FPF3040
VBUS
VOUT
VIN
PMIC
with
BAT Charger &
OTG Boost &
Power Path
VIN_SEL, Other_VIN_Ava
System
Li-Pol
BAT
EN, VIN_SEL, DF_IN
Figure 31.Block Diagram of Input Power Selector for Wireless Charging System
© 2012 Fairchild Semiconductor Corporation
FPF3040 Rev. 2.4.3
11
www.fairchildsemi.com


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Product Specific Package Information
DE
1.96 mm ±0.03 mm
1.76 mm ±0.03 mm
X
0.28 mm
Y
0.38 mm
© 2012 Fairchild Semiconductor Corporation
FPF3040 • Rev. 2.4.3
12
www.fairchildsemi.com


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