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July 2012
FPF3003
IntelliMAX™ Full Functional Input Power Path
Management Switch for Dual-Battery Portable System
Features
2.3V to 5.5V Input Voltage Operating Range
Low RON between Battery and Load
Maximum 50mat VIN = 4.2V
Low RON between Charger and Battery
Maximum 125mat VIN = 4.2V
Maximum DC Current for Load Switch: 2.5A
Maximum DC Current for Charge Switch: 1.5A
Slew Rate Controlled to 30µs Nominal Rise Time
Seamless Break-Before-Make Transition
Quiescent Current: 30µA Typical
Thermal Shutdown
Reverse Current Blocking (RCB) between Battery A
and Battery B
RESET Timer Delay: 7s Typical
ESD Protected:
- Human Body Model: >2.5kV
- Charged Device Model: >1.5kV
- IEC 61000-4-2 Air Discharge: >15kV
- IEC 61000-4-2 Contact Discharge: >8kV
1.6mm X 1.6mm, 16-Bump, 0.4mm Pitch, WLCSP
Applications
Dual-Battery Cell phone
Dual-Battery Portable Equipment
Description
The FPF3003 is a single-chip solution for dual-battery
power-path switching, including integrated P-channel
switches and analog control features. The input voltage
range operates from 2.3V to 5.5V. The device selects
one of two batteries to provide power to the system,
enabling one battery to be charged by the external
battery charger.
The FPF3003 has battery voltage monitoring to
determine if the battery is under voltage. Special driver
and digital circuitry allows the device to switch quickly
between battery A and battery B, which allows hot
swapping of battery packs. Maximum current from
battery to load per channel is limited to a constant 2.5A
and internal thermal shutdown circuits protect the part
during fault conditions.
The FPF3003 is available in a 1.6mm x 1.6mm,
16-bump, Wafer-Level Chip-Scale Package (WLCSP).
Ordering Information
Part Number Top Mark
(Charger-Battery)
Max. RON at 4.2VIN
FPF3003UCX
QW
125m
(Battery-Load)
Max. RON at 4.2VIN
50m
Typical
tR
Package
30µs
16-Bump, 0.4mm Pitch,
1.6mm x 1.6mm WLCSP
© 2011 Fairchild Semiconductor Corporation
FPF3003 • Rev. 1.0.0
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Typical Application Diagram
Functional Block Diagram
Figure 1. Typical Application
Figure 2. Functional Block Diagram
© 2011 Fairchild Semiconductor Corporation
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Pin Configuration
Figure 3. Pin Assignments (Top View)
Figure 4. Pin Assignments (Bottom View)
Pin Description
Pin #
A1
A2
A3, A4
B1
B2
B3,B4
C1
C2
C3,C4
D1
D2
D3
D4
Name
LOBAT
CHGIN
BATA
STAT
BATBID
VOUT
ADPIN
BATAID
BATB
GND
RESETB
BATSEL
CHGSEL
Description
Low Battery A Voltage Input. Connect to the resistive divider to set the trip level for chip-on
moment. If LOBAT is less than 0.8V, VOUT is connected to BATB.
Charging Input. Charging path input.
Supply Input. Battery A voltage input.
Battery Selector Status. Open-drain output. HIGH (Hi-Z) means battery A connects to
VOUT. LOW means battery B connects to VOUT.
Battery B Indicator. Connect this pin with the ID pin at the battery pack of BATB. HIGH
means battery B absent; LOW means battery B present.
Switch Output. Connect to system load.
Adapter Input. 5V input for battery charger.
Battery A Indicator. Connect this pin with the ID pin at the battery pack of BATA. HIGH
means battery A absent; LOW means battery A present.
Supply Input. Battery B voltage input.
Ground
Reset Input. Active LOW. Both system path switches are disconnected from system load.
Battery Selection Input. HIGH means to switch battery B to VOUT; LOW means to switch
battery A to VOUT.
Charge Selection Input. HIGH means to charge battery B: LOW means to charge battery A.
© 2011 Fairchild Semiconductor Corporation
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Absolute Maximum Ratings
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameters
VIN All Pins To GND
Maximum Continuous Switch Current to Load
ISW Maximum Continuous Switch Current to Charger
PD
TSTG
ΘJA
Power Dissipation at TA = 25°C
Operating and Storage Junction Temperature
Thermal Resistance, Junction to Ambient
(1in. Square Pad of 2oz. Copper)
Human Body Model, JESD22-A114
ESD
Charged Device Model, JESD22-C101
Electrostatic Discharge
Capability
Air Discharge (BATA, BATB, ADPIN to
GND), IEC61000-4-2 System Level
Contact Discharge (BATA, BATB, ADPIN
to GND), IEC61000-4-2 System Level
Note:
1. Measured using 2S2P JEDEC std. PCB.
Min.
-0.3
-65
2.5
1.5
15.0
8.0
Max.
6.0
2.5
1.5
1.7
150
72(1)
Unit
V
A
A
W
°C
°C/W
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VIN
TA
Parameters
ADPIN
BATA, BATB
Ambient Operating Temperature
Min.
4.6
2.3
-40
Max.
5.5
5.5
85
Unit
V
V
°C
© 2011 Fairchild Semiconductor Corporation
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Electrical Characteristics
ADPIN=4.6 to 5.5V, VBATA=VBATB=2.3 to 5.5V, TA=-40 to 85°C unless otherwise noted. Typical values are at
ADPIN=5V, CHGIN=VBATA=VBATB=4.2V, RESETB=HIGH, and TA=25°C.
Symbol
Parameters
Condition
Static Characteristics
VADPIN
Adapter Input
Voltage
VADPIN_TH ADPIN Threshold
ADPIN Rising
ADPIN Falling
VBATA,
VBATB
IQ
RON
VIH
VIL
VSTAT_LO
Battery Input Voltage
Quiescent Current
On Resistance to
Load Switch, BATA
or BATB to VOUT
On Resistance to
Charger Switch,
CHGIN to BATA
On Resistance to
Charger Switch,
CHGIN to BATB
Input Logic HIGH
Voltage
Input Logic LOW
Voltage
STAT Logic LOW
Voltage
IOUT=0mA
VBATA=VBATB=5.5V, IOUT=300mA,TA=25°C(2)
VBATA=VBATB=4.2V, IOUT=300mA, TA=25°C
VBATA=VBATB=3.7V, IOUT=300mA,TA=25°C
VBATA=VBATB=2.3V, IOUT=300mA, TA=25°C(2)
VBATA=VBATB=5.5V, ICHG=200mA, TA=25°C(2)
VBATA=VBATB=4.2V, ICHG=200mA, TA=25°C
VBATA=VBATB=3.7V, ICHG=200mA, TA=25°C
VBATA=VBATB=2.3V, ICHG=200mA, TA=25°C(2)
VBATA=VBATB=5.5V, ICHG=200mA, TA=25°C(2)
VBATA=VBATB=4.2V, ICHG=200mA, TA=25°C
VBATA=VBATB=3.7V, ICHG=200mA, TA=25°C
VBATA=VBATB=2.3V, ICHG=200mA, TA=25°C(2)
VBATA=VBATB=2.3V – 5.5V, CHGSEL,
BATSEL
VBATA=VBATB=2.3V – 5.5V, RESETB
VBATA=VBATB=2.3V – 5.5V, BATAID, BATBID
VBATA=VBATB=2.3V – 5.5V, CHGSEL,
BATSEL
VBATA=VBATB=2.3V – 5.5V, RESETB
VBATA=VBATB=2.3V – 5.5V, BATAID, BATBID
ISINK=1mA
VLOBAT
tLOBAT
LOBAT Threshold
LOBAT De-Glitch
Time
VBATA=VBATB=2.3V – 5.5V
VBATA=VBATB=2.3V – 5.5V
Shutdown Threshold
TSD Thermal Shutdown Return from Shutdown
Hysteresis
Output Voltage
VDROOP_OUT Droop while Battery
Switching
VBATA=4.2V, VBATB=4.2V, Switching from
VBATA VBATB, RL=100, COUT=10μF
Min. Typ. Max.
4.6 5.5
4.5
4.2
2.3 5.5
30
34
38 50
43 55
62
66
73 90
80 95
101
92
99 125
105 130
128
0.90
1.15
1.70
0.6
0.8
0.9
0.3
0.8
1.3
150
140
10
100
Unit
V
V
V
μA
m
V
V
V
V
ms
°C
mV
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
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Electrical Characteristics
ADPIN=4.6 to 5.5V, VBATA=VBATB=2.3 to 5.5V, TA=-40 to 85°C unless otherwise noted. Typical values are at
ADPIN=5V, CHGIN=VBATA=VBATB=4.2V, RESETB=HIGH, and TA=25°C.
Symbol
Parameters
Condition
Min.
Reverse Current Blocking between VBATA and VBATB
VT_RCB
RCB Protection Trip
Point
VOUT – VBATA or VBATB
VR_RCB
RCB Protection
Release Trip Point
VBATA or VBATB -VOUT
Hysteresis
Dynamic Characteristics: See Definitions Below
tR
tDON
tON
tF
tDOFF
tOFF
VOUT Rise Time(2,3,4)
Turn-On Delay(2,3,4)
Turn-On Time(2,3,4)
VOUT Fall Time(2,3,5)
Turn-Off Delay(2,3,5)
Turn-Off Time(2,3,5)
VBATA=VBATB=4.2V, RL=100, TA=25°C,
CL=10μF, BATAID=HIGH to LOW,
BATBID=HIGH
VBATA=VBATB=4.2V, RL=100, TA=25°C,
CL=10μf, BATAID=LOW to HIGH,
BATBID=HIGH
tDSEL
Selection Delay(2,3)
VBATA=VBATB=4.2V, RL=100, TA=25°C,
CL=10μF, CHGSEL or BATSEL=LOW to
HIGH
tDRST
RESET Timer
Delay(2,3)
VBATA=VBATB=4.2V, RL=100,TA=25°C,
CL=10μF, RESETB=Floating to LOW
Notes:
2. This parameter is guaranteed by design and characterization; not production tested.
3. tDON/tDOFF/tR/tF is defined in Figure 5.
4. tON=tR + tDON.
5. tOFF=tF + tDOFF.
Typ.
20
30
50
30
5
35
2.5
0.1
2.6
1
7
Max.
Unit
mV
mV
mV
µs
µs
ms
ms
ms
ms
s
© 2011 Fairchild Semiconductor Corporation
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Timing Diagram
Figure 5. ON/OFF Behavior (VBATA=4.2V)
Figure 6. Battery-to-System Path Selection Behavior by BATSEL (VBATA=VBATB=4.2V)
Figure 7. Charging Path Selection Behavior by CHGSEL
(ADPIN=5V, CHGIN=4.2V, VBATA=VBATB=Floating with 1µF)
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Timing Diagrams (Continued)
Figure 8. Transition from VBATA to VBATB Behavior by LOBAT (VBATA=VBATB=4.2V)
Figure 9. System Reset Behavior by RESETB (VBATA=VBATB=4.2V)
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Typical Characteristics
Figure 10. ADPIN vs. Temperature
Figure 11. Supply Current vs. Temperature
Figure 12. Supply Current vs. Supply Voltage
Figure 13. RON (VBATA or VBATB to VOUT)
vs. Temperature
Figure 14. RON (VBATA or VBATB to VOUT)
vs. Supply Voltage
Figure 15. RON (CHGIN to VBATA) vs. Temperature
© 2011 Fairchild Semiconductor Corporation
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Typical Characteristics
Figure 16. RON (CHGIN to VBATA) vs. Supply Voltage Figure 17. RON (CHGIN to VBATB) vs. Temperature
Figure 18. RON (CHGIN to VBATB) vs. Supply Voltage
Figure 19. CHGSEL vs. Temperature
Figure 20. CHGSEL vs. ADPIN Voltage
Figure 21. BATSEL vs. Temperature
© 2011 Fairchild Semiconductor Corporation
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Typical Characteristics
Figure 22. BATSEL vs. Supply Voltage
Figure 23. LOBAT vs. Temperature
Figure 24. STAT LOW vs. Temperature
Figure 25. RCB (VBATA and VOUT) vs. Temperature
Figure 26. RCB (VBATB and VOUT) vs. Temperature
Figure 27. Turn-On Response
(VBATA=4.2V, COUT=10µF, RL=100)
© 2011 Fairchild Semiconductor Corporation
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Typical Characteristics
Figure 28. Turn-Off Response
(VBATA=4.2V, COUT=10µF, RL=100)
Figure 29. Battery Selection by BATSEL = HIGH
LOW (VBATA=4V, VBATB=4.2V, COUT=100µF, RL=100)
Figure 30. Battery Selection by BATSEL = LOW Figure 31. Charge Path Selection by CHGSEL = HIGH
HIGH (VBATA=4V, VBATB=4.2V, COUT=10µF, RL=100) LOW (VCHGIN=4V, VBATA=VBATB=Floating with 1µF)
Figure 32. Charge Path Selection by CHGSEL = HIGH Figure 33. Battery Selection by LOBAT=HIGH
LOW (VCHGIN=4V, BATA=BATB=Floating with 1µF) LOW (VBATA=3.8V, VBATB=4.2V, COUT=100µF, RL=100)
© 2011 Fairchild Semiconductor Corporation
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Typical Characteristics
Figure 34. System Reset by RESETB: HIGH LOW (VBATA=VBATB=4.2V, COUT=100µF, RL=100)
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Operation and Application Information
The FPF3003 is a low-RON, P-channel-based, input-
source-selection power management switch for dual-
battery systems. The FPF3003 input operating range is
from 2.3V to 5.5V on BATA and BATB, while ADPIN has
a range of 4.6V to 5.5V.
The FPF3003 controls the charging path from the
charger to the battery with up to 1.5A and the
discharging path from the battery to system load with up
to 2.5A. The system or PMIC selects one of two
batteries to provide power and enables one of the
batteries to be charged by the external battery charger.
The FPF3003 has 30µs slew-rate control to reduce
inrush current when engaged and thermal shutdown
protection for reliable system operation.
The internal circuit is powered from the highest voltage
source among BATA, BATB, and ADPIN.
Battery Presence Detection
The FPF3003 monitors whether or not a battery is
present via the BATAID and BATBID pins. If any of
these pins are LOW; FPF3003 recognizes the battery is
present. Each pin is connected with an internal LDO
output, so no pull-up resistor is required.
Output Capacitor
During battery source transition, voltage droop depends
on output capacitance and load current condition.
Advanced break-before-make operation minimizes the
droop with minimum capacitance. At least 10µF is a
good starting value in design.
Primary Battery Under-Voltage Set
FPF3003 monitors the primary battery of BATA for
under-voltage condition. Once under-voltage condition
is confirmed, the system power source changes from
BATA to valid BATB automatically.
The under-voltage threshold level can be programmed
with 0.8V of LOBAT and R divider (R1 and R2) as:
1
2
=
_
0.8
−1
(1)
where BATA_LO = Low BATA threshold to set.
If 3.4V of BATA is desired, R1/R2=3.25. If R2 is chosen
1M, R1 is 3.25M. Higher R2 is recommended to
reduce leakage current from BATA.
Battery Selection
The load path can be controlled by the BATSEL pin.
When BATSEL is LOW, the system is powered from
BATA. When BATSEL is HIGH, BATB powers the system.
Figure 36 is state diagram showing how the power path
from battery to system is determined.
Power On
from ADPIN, BATA, or BATB
RESETB = HIGH
N
VOUT Floating
Switch to the present battery
Y
Y
Either BATAID or
BATBID = HIGH
N
Both BATAID and
BATBID = LOW
Y
LOBAT > 0.8V
N
N
Y
BATSEL = LOW
N
Switch to BATB
Y
Switch to BATA
Figure 36. Power Path from Battery to System
The open-drain STAT pin is used to determine which
battery powers the system. STAT becomes LOW if
BATB is connected to the system. STAT is HIGH (HI-Z)
if BATA is connected.
Figure 35. BATA Under-Voltage Level Setting
LOBAT has a 1.3ms of deglitch time to ensure BATA is
in true under-voltage rather than transient battery
voltage drop during GSM transmission operation.
© 2011 Fairchild Semiconductor Corporation
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Battery Charging Path Selection
The charging path can be controlled by the CHGSEL
pin. When CHGSEL is LOW, BATA can be charged
from the charger. When CHGSEL is HIGH, BATB can
be charged from the charger.
System RESET
The RESETB pin allows the system to be turned off
without detaching the battery pack. It has typical 7s
delay to avoid transient abnormal signal.
Board Layout
For best performance, all power traces (BATA, BATB,
CHGIN, ADPIN, and VOUT) should be as short as
possible to minimize the parasitic electrical effects and
the case-to-ambient thermal impedance. The output
capacitor should be placed close to the device to
minimize parasitic trace inductance.
Figure 37. Battery Charging Path
© 2011 Fairchild Semiconductor Corporation
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Packaging Information
0.03 C
2X
E
AF
B
BALL A1
INDEX AREA
D
0.03 C
2X
TOP VIEW
0.05 C
0.06 C
0.625
0.547
E
0.40 (Ø0.20)
A1 Cu Pad
0.40 (Ø0.30) Solder
Mask Opening
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
0.378±0.018
0.208±0.021
C SEATING
PLANE D
SIDE VIEWS
0.40
0.40
1234
0.005 C A B
Ø0.260±0.02
16X
D
C
B (Y) ±0.018
A
F
(X) ±0.018
BOTTOM VIEW
NOTES:
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCE
PER ASME Y14.5M, 1994.
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS
±39 MICRONS (547-625 MICRONS).
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
G. DRAWING FILNAME: MKT-UC016AArev2.
Figure 38. 1.6mmx1.6mm WLCSP, 16-Bumps 0.4mm Pitch
Product-Specific Dimensions
Product
D
FPF3003UCX
1560μm ±30μm
E
1560μm ±30μm
X
180μm
Y
180μm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
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