Fairchild Semiconductor Electronic Components Datasheet



FPF1039

Slew-Rate-Controlled Load Switch


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April 2015
FPF1039
Low On-Resistance, Slew-Rate-Controlled Load Switch
Features
1.2 V to 5.5 V Input Voltage Operating Range
Typical RON:
20 mΩ at VIN=5.5 V
21 mΩ at VIN=4.5 V
37 mΩ at VIN=1.8 V
75 mΩ at VIN=1.2 V
Slew Rate / Inrush Control with tR: 2.7 ms (Typical)
3.5 A Maximum Continuous Current Capability
Output Capacitor Discharge Function
Low <1 µA Shutdown Current
ESD Protected: Above 8 kV HBM, 1.5 kV CDM
GPIO / CMOS-Compatible Enable Circuitry
Applications
HDD, Storage, and Solid-State Memory Devices
Portable Media Devices, UMPC, Tablets, MIDs
Wireless LAN Cards and Modules
SLR Digital Cameras
Portable Medical Devices
GPS and Navigation Equipment
Industrial Handheld and Enterprise Equipment
Description
The FPF1039 advanced load-management switch target
applications requiring a highly integrated solution for
disconnecting loads powered from DC power rail (<6 V)
with stringent shutdown current targets and high load
capacitances (up to 200 µF). The FPF1039 consists of
slew-rate controlled low-impedance MOSFET switch
(21 typical) and other integrated analog features.
The slew-rate controlled turn-on characteristic prevents
inrush current and the resulting excessive voltage droop
on power rails.
This device has exceptionally low shutdown current
drain (<1 µA maximum) that facilitates compliance in
low standby power applications. The input voltage range
operates from 1.2 V to 5.5 V DC to support a wide range
of applications in consumer, optical, medical, storage,
portable, and industrial device power management.
Switch control is managed by a logic input (active HIGH)
capable of interfacing directly with low-voltage control
signal / GPIO with no external pull-up required. The
device is packaged in advanced fully “green1mm
x1.5 mm Wafer-Level Chip-Scale Packaging (WLCSP);
providing excellent thermal conductivity, small footprint,
and low electrical resistance for wider application usage.
Ordering Information
Part Number
Top
Mark
Switch
RON
(Typical)
at 4.5 VIN
FPF1039UCX QF
21
FPF1039BUCX QF
21
Input
Buffer
CMOS
CMOS
Output ON Pin
Discharge Activity
tR
Package
65Ω
Active HIGH
2.7 ms
6-Bump, WLCSP, 1.0 mm
x 1.5 mm, 0.5 mm Pitch
6-Bump, WLCSP with
65Ω
Active HIGH
2.7 ms
Backside Laminate,
1.0 mm x 1.5 mm,
0.5 mm Pitch
© 2010 Fairchild Semiconductor Corporation
FPF1039 • Rev. 1.5
www.fairchildsemi.com


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Application Diagram
VIN
VIN:1.2V 5.5V
OFF ON
CIN
VIN VOUT
FPF1039
ON
GND
Figure 1. Typical Application
VOUT
COUT: 0 200µF
Functional Block Diagram
VIN
ON
R
FPF1039
CONTROL
LOGIC
ESD Protection
Turn-On Slew Rate
Controlled Driver
Output Discharge
VOUT
Figure 2. Functional Block Diagram
© 2010 Fairchild Semiconductor Corporation
FPF1039 • Rev. 1.5
2
www.fairchildsemi.com


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Pin Configuration
VOUT A1
A2 VIN
VOUT B1
B2 VIN
GND C1
C2 ON
Figure 3. Top View
VIN A2
A1 VOUT
VIN B2
B1 VOUT
ON C2
C1 GND
Figure 4. Bottom View
Pin Definitions
Pin #
A1, B1
A2, B2
C1
C2
Name
VOUT
VIN
GND
ON
Description
Switch Output
Supply Input: Input to the Power Switch
Ground
ON/OFF Control, Active High - GPIO Compatible
© 2010 Fairchild Semiconductor Corporation
FPF1039 • Rev. 1.5
3
www.fairchildsemi.com


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Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameters
VIN
ISW
PD
TSTG
TA
VIN, VOUT, VON to GND
Maximum Continuous Switch Current
Power Dissipation at TA=25°C
Storage Junction Temperature
Operating Temperature Range
JA Thermal Resistance, Junction-to-Ambient
ESD
Electrostatic Discharge Capability
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
Notes:
1. Measured using 2S2P JEDEC std. PCB.
2. Measured using 2S2P JEDEC PCB COLD PLATE method.
Min.
-0.3
-65
-40
8.0
1.5
Max.
6.0
3.5
1.2
+150
+85
85(1)
110(2)
Unit
V
A
W
°C
°C
°C/W
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameters
VIN Input Voltage
TA Ambient Operating Temperature
Min.
1.2
-40
Max.
5.5
+85
Unit
V
°C
© 2010 Fairchild Semiconductor Corporation
FPF1039 • Rev. 1.5
4
www.fairchildsemi.com


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Electrical Characteristics
Unless otherwise noted, VIN=1.2 to 5.5V and TA=-40 to +85°C; typical values are at VIN=4.5V and TA=25°C.
Symbol
Parameters
Conditions
Min. Typ. Max. Units
Basic Operation
VIN Input Voltage
1.2
IQ(OFF) Off Supply Current
VON=GND, VOUT=Open
ISD Shutdown Current
VON=GND, VOUT=GND
IQ Quiescent Current
IOUT=0 mA
VIN=5.5 V, IOUT=1 A(3)
RON On Resistance
VIN=4.5 V, IOUT=1 A, TA=25°C
VIN=3.3 V, IOUT=500 mA(3)
VIN=2.5 V, IOUT=500 mA(3)
VIN=1.8 V, IOUT=250 mA(3)
VIN=1.2 V, IOUT=250 mA, TA=25°C
RPD
Output Discharge RPULL DOWN
VIN=4.5 V, VON=0 V, IFORCE=20 mA,
TA=25°C
VIH On Input Logic HIGH Voltage
1.0
VIL On Input Logic LOW Voltage
ION On Input Leakage
Dynamic Characteristics
tDON
tR
tON
tDOFF
tF
tOFF
Turn-On Delay(4)
VOUT Rise Time(4)
Turn-On Time(6)
Turn-Off Delay(4,5)
VOUT Fall Time(4,5)
Turn-Off (5,7)
VIN=4.5 V, RL=5 Ω, CL=100 µF,
TA=25°C
VIN=4.5 V, RL=150 Ω, CL=100 µF,
TA=25°C (5)
Notes:
3. This parameter is guaranteed by design and characterization; not production tested.
4. tDON/tDOFF/tR/tF are defined in Figure 32.
5. Output discharge enabled during off-state.
6. tON=tR + tDON
7. tOFF=tF + tDOFF
0.2
5.5
20
21
24
28
37
75
65
1.7
2.7
4.4
0.5
10.0
10.5
5.5
1.0
1.0
8.0
24
25
29
35
45
100
85
0.4
1.5
V
μA
μA
μA
Ω
V
V
μA
ms
ms
ms
ms
ms
ms
© 2010 Fairchild Semiconductor Corporation
FPF1039 • Rev. 1.5
5
www.fairchildsemi.com


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Typical Characteristics
Figure 5. Shutdown Current vs. Temperature
Figure 6. Shutdown Current vs. Supply Voltage
Figure 7. Off Supply Current vs. Temperature
(VOUT = 0 V)
Figure 8. Off Supply Current vs. Supply Voltage
(VOUT = 0 V)
Figure 9. Quiescent Current vs. Temperature
Figure 10. Quiescent Current vs. Supply Voltage
© 2010 Fairchild Semiconductor Corporation
FPF1039 • Rev. 1.5
6
www.fairchildsemi.com


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Typical Characteristics (Continued)
Figure 11. Quiescent Current vs. On Voltage
(VIN = 4.5 V)
Figure 12. Quiescent Current vs. On Voltage
(VIN = 5.5 V)
Figure 13. Output Discharge Resistor RPD
vs. Temperature
90
80
70
60
50
40
30
20
10
0
-40
VIN = 1.2V
VIN = 4.5V
VIN = 5.5V
ON = VIN
IOUT=0.25A@1.2V
IOUT=1A@4.5V&5.5V
-15 10 35 60
TJ, JUNCTION TEMPERATURE (°C)
85
Figure 15. RON vs. Temperature
Figure 14. Output Discharge Resistor RPD
vs. Supply Voltage
Figure 16. RON vs. Supply Voltage
© 2010 Fairchild Semiconductor Corporation
FPF1039 • Rev. 1.5
7
www.fairchildsemi.com


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Typical Characteristics (Continued)
Figure 17. On Pin Threshold Low vs. Temperature
Figure 18. On Pin Threshold Low vs. VIN
Figure 19. On Pin Threshold High vs. Temperature
Figure 20. On Pin Threshold High vs. VIN
Figure 21. On Pin Threshold vs. Supply Voltage
Figure 22. ISW vs. (VIN-VOUT) SOA
© 2010 Fairchild Semiconductor Corporation
FPF1039 • Rev. 1.5
Figure 23. tR/tF vs. Temperature
8
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Typical Characteristics (Continued)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40
Tr
Tdon
VIN = 4.5V
CL = 100uF
RL = 5 Ohm
-15 10 35 60
TJ, JUNCTION TEMPERATURE (°C)
85
Figure 24. tR/tDON vs. Temperature
Figure 25. tR vs. Supply Voltage
Figure 26. tR vs. Supply Voltage
4.50
4.00
3.50 +85C
3.00 +25C
-40C
2.50
2.00
1.50
VON
1.00
0.50
0.00
0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00
Time (ms)
Figure 27. Turn-On Response
(VIN=4.5 V, CIN=10 µF, CL=1 µF, RL=50 )
4.50 4.5
4.00
+85C
3.50
3.00 +25C
-40C
2.50
2.00
4
3.5
3
2.5
+25C
2
1.50
VON
1.00
0.50
1.5
1
VON
0.5
0.00
0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 0
0
Time (ms)
5
10 15 20 25 30 35
Time (ms)
Figure 28. Turn-On Response
(VIN=4.5 V, CIN=10 µF, CL=100 µF, RL=5 )
Figure 29. Turn-Off Response
(VIN=4.5 V, CIN=10 µF, CL=100 µF, without External RL)
© 2010 Fairchild Semiconductor Corporation
FPF1039 • Rev. 1.5
9
www.fairchildsemi.com


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Typical Characteristics (Continued)
10.000
1.000
100mF
0.100
10mF
0.010
1mF
100
10
1
0.1
0.01
500
50
5
0.001
1
10 100
RLOAD ()
1000
10000
Figure 30. Fall Time as a Function of External
Resistive Load (CL=1 µF, 10 µF, and 100 µF)
0.001
0.1
1 10 100
CLOAD (mF)
1000
Figure 31. Fall Time as a Function of External
Capacitive Load (RL=5 , 50 , and 500 )
VOUT
90%
10%
tR
VON
50%
4.5V
90%
tF
10%
50%
VOUT
10%
tDON
90%
tDOFF
Figure 32. Timing Diagram
© 2010 Fairchild Semiconductor Corporation
FPF1039 • Rev. 1.5
10
www.fairchildsemi.com


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Application Information
Input Capacitor
This IntelliMAX™ switch doesn’t require an input
capacitor. To reduce device inrush current, a 0.1 µF
ceramic capacitor, CIN, is recommended close to the
VIN pin. A higher value of CIN can be used to reduce the
voltage drop experienced as the switch is turned on into
a large capacitive load.
Output Capacitor
While this switch works without an output capacitor: if
parasitic board inductance forces VOUT below GND
when switching off; a 0.1 µF capacitor, COUT, should be
placed between VOUT and GND.
Fall Time
Device output fall time can be calculated based on RC
constant of the external components as follows:
tF RL CL 2.2
(1)
where tF is 90% to 10% fall time, RL is output load,
and CL is output capacitor.
The same equation works for a device with a pull-down
output resistor. RL is replaced by a parallel connected
pull-down and an external output resistor combination as:
tF
RL
RL
RPD
RPD
CL
2.2
(2)
where tF is 90% to 10% fall time, RL is output load,
RPD=65 is output pull-down resistor, and CL is the
output capacitor.
Resistive Output Load
If resistive output load is missing, the IntelliMAX switch
without a pull-down output resistor does not discharge
the output voltage. Output voltage drop depends, in that
case, mainly on external device leaks.
Application Specifics
At maximum operational voltage (VIN=5.5 V), device
inrush current might be higher than expected. Spike
current should be taken into account if VIN>5 V and the
output capacitor is much larger than the input capacitor.
Input current can be calculated as:
IIN(t)
VOUT (t)
RLOAD
(CLOAD
CIN
)
dVOUT
dt
(t)
(3)
where switch and wire resistances are neglected and
capacitors are assumed ideal.
Estimating VOUT(t)=VIN/10 and using experimental
formula for slew rate (dVOUT(t)/dt), spike current can be
written as:
max IIN
VIN
10RLOAD
CLOAD
CIN0.05VIN
0.255 
(4)
where supply voltage VIN is in volts, capacitances are
in micro farads, and resistance is in ohms.
Example: If VIN=5.5V, CLOAD=100 µF, CIN=10 µF, and
RLOAD=50 ; calculate the spike current by:
max(
IIN)
5.5
1050
(100
10)(0.055.5
0.255 )A
1.8A
(5)
Maximum spike current is 1.8 A, while average ramp-
up current is:
IIN(t)
VOUT (t)
RLOAD
(CLOAD
CIN )
dVIN(t)
dt
2.75 / 50 100 0.0022 0.275 A
(6)
Output Discharge
FPF1039 contains a 65 Ω on-chip pull-down resistor for
quick output discharge. The resistor is activated when
the switch is turned off.
Recommended Layout
For best thermal performance and minimal inductance
and parasitic effects, it is recommended to keep input
and output traces short and capacitors as close to the
device as possible. Figure 34 is a recommended layout
for this device to achieve optimum performance.
Vin Vout
VIN FPF1039
CIN OFF ON ON
GND
+
CLOAD
RLOAD
Figure 33. Device Setup
© 2010 Fairchild Semiconductor Corporation
FPF1039 • Rev. 1.5
Figure 34. Recommended Land Pattern, Layout
www.fairchildsemi.com
11


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Physical Dimensions
0.03 C
2X
E AF
B
BALL A1
INDEX AREA
D
TOP VIEW
0.03 C
2X
0.05 C
0.06 C
0.625
0.539
E
(Ø0.350)
SOLDER MASK
OPENING
A1
(Ø0.250)
Cu Pad
(1.00)
(0.50)
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
0.332±0.018
0.250±0.025
C SEATING PLANE D
SIDE VIEWS
0.50
0.005 C A B
Ø0.315 +/- .025
6X
1.00
0.50
C
B (Y) ±0.018
A
12
F
(X) ±0.018
BOTTOM VIEW
NOTES:
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCE
PER ASMEY14.5M, 1994.
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
E. PACKAGE NOMINAL HEIGHT IS 582 MICRONS
±43 MICRONS (539-625 MICRONS).
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
G. DRAWING FILNAME: MKT-UC006AFrev2.
Figure 35. 6 Ball, 1.0 x 1.5 mm Wafer-Level Chip-Scale Packaging (WLCSP)
© 2010 Fairchild Semiconductor Corporation
FPF1039 • Rev. 1.5
12
www.fairchildsemi.com


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Nominal Values
Bump
Pitch
Overall Package
Height
0.5 mm
0.582 mm
Silicon
Thickness
0.332 mm
Solder Bump
Height
0.250 mm
Product-Specific Dimensions
Product
D
FPF1039UCX
FPF1039BUCX
1.46 mm ±0.03
1.46 mm ±0.03
E
0.96 mm ±0.03
0.96 mm ±0.03
X
0.230 mm
0.230 mm
Solder Bump
Diameter
0.315 mm
Y
0.230 mm
0.230 mm
© 2010 Fairchild Semiconductor Corporation
FPF1039 • Rev. 1.5
13
www.fairchildsemi.com


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FPF1039 • Rev. 1.5
14
www.fairchildsemi.com


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