FPF1038 Datasheet PDF
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November 2013
FPF1038
Low On-Resistance, Slew-Rate-Controlled Load Switch
Features
1.2 V to 5.5 V Input Voltage Operating Range
Typical RON:
20 mΩ at VIN=5.5 V
21 mΩ at VIN=4.5 V
37 mΩ at VIN=1.8 V
75 mΩ at VIN=1.2 V
Slew Rate / Inrush Control with tR: 2.7 ms (Typical)
3.5 A Maximum Continuous Current Capability
Low <1 µA Shutdown Current
ESD Protected: Above 8 kV HBM, 1.5 kV CDM
GPIO / CMOS-Compatible Enable Circuitry
Applications
HDD, Storage, and Solid-State Memory Devices
Portable Media Devices, UMPC, Tablets, MIDs
Wireless LAN Cards and Modules
SLR Digital Cameras
Portable Medical Devices
GPS and Navigation Equipment
Industrial Handheld and Enterprise Equipment
Description
The FPF1038 advanced load-management switch target
applications requiring a highly integrated solution for
disconnecting loads powered from DC power rail (<6 V)
with stringent shutdown current targets and high load
capacitances (up to 200 µF). The FPF1038 consists of
slew-rate controlled low-impedance MOSFET switch
(21 typical) and other integrated analog features.
The slew-rate controlled turn-on characteristic prevents
inrush current and the resulting excessive voltage droop
on power rails.
These devices have exceptionally low shutdown current
drain (<1 µA maximum) that facilitates compliance in
low standby power applications. The input voltage range
operates from 1.2 V to 5.5 V DC to support a wide range
of applications in consumer, optical, medical, storage,
portable, and industrial device power management.
Switch control is managed by a logic input (active HIGH)
capable of interfacing directly with low-voltage control
signal / GPIO with no external pull-up required. The
device is packaged in advanced fully “green” 1mm
x1.5 mm Wafer-Level Chip-Scale Packaging (WLCSP);
providing excellent thermal conductivity, small footprint,
and low electrical resistance for wider application usage.
Ordering Information
Part Number
Top
Mark
Switch RON
(Typical)
at 4.5 VIN
FPF1038UCX QE
21
Input Output ON Pin
Buffer Discharge Activity
tR
Package
CMOS
NA
Active
HIGH
2.7 ms
6-Bump, WLCSP, 1.0 mm
x 1.5 mm, 0.5 mm Pitch
© 2010 Fairchild Semiconductor Corporation
FPF1038 • Rev. 1.0.6
www.fairchildsemi.com


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Application Diagram
VIN
VIN:1.2V – 5.5V
OFF ON
CIN
VIN VOUT
FPF1038
ON
GND
Figure 1. Typical Application
VOUT
COUT: 0 – 200µF
Functional Block Diagram
VIN
ON
R
FPF1038
CONTROL
LOGIC
ESD Protection
Turn-On Slew Rate
Controlled Driver
VOUT
GND
Figure 2. Functional Block Diagram
© 2010 Fairchild Semiconductor Corporation
FPF1038 • Rev. 1.0.6
2
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Pin Configuration
VOUT A1
A2 VIN
VOUT B1
B2 VIN
GND C1
C2 ON
Figure 3. Top View
VIN A2
A1 VOUT
VIN B2
B1 VOUT
ON C2
C1 GND
Figure 4. Bottom View
Pin Definitions
Pin #
A1, B1
A2, B2
C1
C2
Name
VOUT
VIN
GND
ON
Description
Switch Output
Supply Input: Input to the Power Switch
Ground
ON/OFF Control, Active High - GPIO Compatible
© 2010 Fairchild Semiconductor Corporation
FPF1038 • Rev. 1.0.6
3
www.fairchildsemi.com


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Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameters
VIN
ISW
PD
TSTG
TA
VIN, VOUT, VON to GND
Maximum Continuous Switch Current
Power Dissipation at TA=25°C
Storage Junction Temperature
Operating Temperature Range
ΘJA Thermal Resistance, Junction-to-Ambient
Human Body Model, JESD22-A114
ESD Electrostatic Discharge Capability
Charged Device Model, JESD22-C101
Notes:
1. Measured using 2S2P JEDEC std. PCB.
2. Measured using 2S2P JEDEC PCB COLD PLATE method.
Min.
-0.3
-65
-40
8.0
1.5
Max.
6.0
3.5
1.2
+150
+85
85(1)
110(2)
Unit
V
A
W
°C
°C
°C/W
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameters
VIN Input Voltage
TA Ambient Operating Temperature
Min.
1.2
-40
Max.
5.5
+85
Unit
V
°C
© 2010 Fairchild Semiconductor Corporation
FPF1038 • Rev. 1.0.6
4
www.fairchildsemi.com


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Electrical Characteristics
Unless otherwise noted, VIN=1.2 to 5.5 V and TA=-40 to +85°C; typical values are at VIN=4.5 V and TA=25°C.
Symbol
Parameters
Conditions
Min. Typ. Max. Units
Basic Operation
VIN Input Voltage
1.2
IQ(OFF) Off Supply Current
VON=GND, VOUT=Open
ISD Shutdown Current
VON=GND, VOUT=GND
IQ Quiescent Current
IOUT=0 mA
VIN=5.5 V, IOUT=1 A(3)
RON On Resistance
VIN=4.5 V, IOUT=1 A, TA=25°C
VIN=3.3 V, IOUT=500 mA(3)
VIN=2.5 V, IOUT=500 mA(3)
VIN=1.8 V, IOUT=250 mA(3)
VIN=1.2 V, IOUT=250 mA, TA=25°C
VIH On Input Logic HIGH Voltage
1.0
VIL On Input Logic LOW Voltage
ION On Input Leakage
Dynamic Characteristics
tDON
tR
tON
tDOFF
tF
tOFF
Turn-On Delay(4)
VOUT Rise Time(4)
Turn-On Time(6)
Turn-Off Delay(4)
VOUT Fall Time(4)
Turn-Off(7)
VIN=4.5 V, RL=5 Ω, CL=100 µF,
TA=25°C
VIN=4.5 V, RL=150 Ω, CL=100 µF,
TA=25°C, No Load Discharge
Notes:
3. This parameter is guaranteed by design and characterization; not production tested.
4. tDON/tDOFF/tR/tF are defined in Figure 27.
5. Output discharge enabled during off-state.
6. tON=tR + tDON
7. tOFF=tF + tDOFF
0.2
5.5
20
21
24
28
37
75
1.7
2.7
4.4
2.0
30.0
32.0
5.5
1.0
1.0
8.0
24
25
29
35
45
100
0.4
1.0
V
μA
μA
μA
V
V
μA
ms
ms
ms
ms
ms
ms
© 2010 Fairchild Semiconductor Corporation
FPF1038 • Rev. 1.0.6
5
www.fairchildsemi.com


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Typical Characteristics
Figure 5. Shutdown Current vs. Temperature
Figure 6. Shutdown Current vs. Supply Voltage
Figure 7. Off Supply Current vs. Temperature
(VOUT Floating)
Figure 8. Off Supply Current vs. Supply Voltage
(VOUT Floating)
Figure 9. Quiescent Current vs. Temperature
Figure 10. Quiescent Current vs. Supply Voltage
© 2010 Fairchild Semiconductor Corporation
FPF1038 • Rev. 1.0.6
6
www.fairchildsemi.com


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Typical Characteristics (Continued)
Figure 11. Quiescent Current vs. On Voltage
(VIN = 4.5V)
90
80
70
60
50
40
30
20
10
0
-40
VIN = 1.2V
VIN = 4.5V
VIN = 5.5V
ON = VIN
IOUT=0.25A@1.2V
IOUT=1A@4.5V&5.5V
-15 10 35 60
TJ, JUNCTION TEMPERATURE (°C)
85
Figure 13. RON vs. Temperature
Figure 12. Quiescent Current vs. On Voltage
(VIN = 5.5V)
Figure 14. RON vs. Supply Voltage
Figure 15. On Pin Threshold Low vs. Temperature
Figure 16. On Pin Threshold Low vs. VIN
© 2010 Fairchild Semiconductor Corporation
FPF1038 • Rev. 1.0.6
7
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Typical Characteristics (Continued)
Figure 17. On Pin Threshold High vs. Temperature
Figure 18. On Pin Threshold High vs. VIN
Figure 19. On Pin Threshold vs. Supply Voltage
Figure 20. ISW vs. (VIN-VOUT) — SOA
Figure 21. tR/tDON vs. Temperature
Figure 22. tR/tF vs. Temperature
© 2010 Fairchild Semiconductor Corporation
FPF1038 • Rev. 1.0.6
8
www.fairchildsemi.com


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Typical Characteristics (Continued)
Figure 23. tR vs. Supply Voltage
Figure 24. tR vs. Supply Voltage
4.50
4.00
3.50
3.00
2.50
2.00
1.50
VON
1.00
+85C
+25C
-40C
4.50
4.00
3.50
3.00
2.50
2.00
1.50
VON
1.00
+85C
+25C
-40C
0.50 0.50
0.00 0.00
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00 0.00
1.00
2.00 3.00 4.00
5.00 6.00 7.00
Time (ms)
Time (ms)
Figure 25. Turn-On Response (VIN=4.5 V, CIN=10 µF, Figure 26. Turn-On Response (VIN=4.5 V, CIN=10 µF,
CL=1 µF, RL=50 )
CL=100 µF, RL=5 )
VOUT
90%
10%
tR
VON
50%
4.5V
90%
tF
10%
50%
VOUT
10%
tDON
90%
tDOFF
Figure 27. Timing Diagram
© 2010 Fairchild Semiconductor Corporation
FPF1038 • Rev. 1.0.6
9
www.fairchildsemi.com


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Application Information
Input Capacitor
This IntelliMAX™ switch doesn’t require an input
capacitor. To reduce device inrush current, a 0.1 µF
ceramic capacitor, CIN, is recommended close to the
VIN pin. A higher value of CIN can be used to reduce the
voltage drop experienced as the switch is turned on into
a large capacitive load.
Output Capacitor
While this switch works without an output capacitor: if
parasitic board inductance forces VOUT below GND
when switching off; a 0.1 µF capacitor, COUT, should be
placed between VOUT and GND.
Fall Time
Device output fall time can be calculated based on RC
constant of the external components as follows:
tF = RL × CL × 2.2
(1)
where tF is 90% to 10% fall time, RL is output load,
and CL is output capacitor.
The same equation works for a device with a pull-down
output resistor. RL is replaced by a parallel connected
pull-down and an external output resistor combination as:
tF
=
RL
RL
× RPD
+ RPD
× CL
× 2.2
(2)
where tF is 90% to 10% fall time, RL is output load,
RPD=65 is output pull-down resistor, and CL is the
output capacitor.
Resistive Output Load
If resistive output load is missing, the IntelliMAX switch
without a pull-down output resistor does not discharge
the output voltage. Output voltage drop depends, in that
case, mainly on external device leaks.
Application Specifics
At maximum operational voltage (VIN=5.5 V), device
inrush current might be higher than expected. Spike
current should be taken into account if VIN>5 V and the
output capacitor is much larger than the input capacitor.
Input current can be calculated as:
IIN(t)
VOUT (t)
RLOAD
+ (CLOAD
CIN
)
dVOUT
dt
(t
)
(3)
where switch and wire resistances are neglected and
capacitors are assumed ideal.
Estimating VOUT(t)=VIN/10 and using experimental
formula for slew rate (dVOUT(t)/dt), spike current can be
written as:
max(IIN) =
VIN
10RLOAD
+ (CLOAD
CIN )0.05VIN
0.255
(4)
where supply voltage VIN is in volts, capacitances are
in micro farads, and resistance is in ohms.
Example: If VIN=5.5 V, CLOAD=100 µF, CIN=10 µF, and
RLOAD=50 ; calculate the spike current by:
max(IIN )
=
5.5
1050
+
(100
10)(0.055.5
0.255)A
=
1.8A
(5)
Maximum spike current is 1.8 A, while average ramp-
up current is:
IIN(t)
VOUT (t )
RLOAD
+
(CLOAD
CIN
)
dVIN(t)
dt
2.75 / 50 + 1000.0022 = 0.275A
(6)
Recommended Layout
For best thermal performance and minimal inductance
and parasitic effects, it is recommended to keep input
and output traces short and capacitors as close to the
device as possible. Figure 29 is a recommended layout
for this device to achieve optimum performance.
Vin Vout
VIN FPF1038
CIN OFF ON ON
GND
+
CLOAD
RLOAD
Figure 28. Device Setup
Figure 29. Recommended Land Pattern, Layout
© 2010 Fairchild Semiconductor Corporation
FPF1038 • Rev. 1.0.6
10
www.fairchildsemi.com


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Physical Dimensions
0.03 C
2X
E AF
B
BALL A1
INDEX AREA
D
TOP VIEW
0.03 C
2X
0.05 C
0.06 C
0.625
0.539
E
(Ø0.350)
SOLDER MASK
OPENING
A1
(Ø0.250)
Cu Pad
(1.00)
(0.50)
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
0.332±0.018
0.250±0.025
C SEATING PLANE D
SIDE VIEWS
0.50
0.005 C A B
Ø0.315 +/- .025
6X
1.00
0.50
C
B (Y) ±0.018
A
12
F
(X) ±0.018
BOTTOM VIEW
NOTES:
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCE
PER ASMEY14.5M, 1994.
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
E. PACKAGE NOMINAL HEIGHT IS 582 MICRONS
±43 MICRONS (539-625 MICRONS).
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
G. DRAWING FILNAME: MKT-UC006AFrev2.
Figure 30. 6 Ball, 1.0 x 1.5 mm Wafer-Level Chip-Scale Packaging (WLCSP)
Nominal Values
Bump
Pitch
Overall Package
Height
Silicon
Thickness
Solder Bump
Height
Solder Bump
Diameter
0.5 mm
0.582 mm
0.332 mm
0.250 mm
0.315 mm
Product-Specific Dimensions
Product
D
FPF1038UCX
1.5 mm ±0.03
E
1.0 mm ±0.03
X
0.240 mm
Y
0.240 mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
FPF1038 • Rev. 1.0.6
11
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12
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