Fairchild Semiconductor Electronic Components Datasheet



FPF1320

Dual-Input Single-Output Advanced Power Switch


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September 2013
FPF1320 / FPF1321
IntelliMAX™ Dual-Input Single-Output Advanced Power
Switch with True Reverse-Current Blocking
Features
DISO Load Switches
Input Supply Operating Range: 1.5 V ~ 5.5 V
RON 50 mat VIN=3.3 V Per Channel (Typical)
True Reverse-Current Blocking (TRCB)
Fixed Slew Rate Controlled 130 µs for < 1 µF COUT
ISW: 1.5 A Per Channel (Maximum)
Quick Discharge Feature on FPF1321
Logic CMOS IO Meets JESD76 Standard for GPIO
Interface and Related Power Supply Requirements
ESD Protected:
- Human Body Model: >6 kV
- Charged Device Model: >1.5 kV
- IEC 61000-4-2 Air Discharge: >15 kV
- IEC 61000-4-2 Contact Discharge: >8 kV
Applications
Smart phones / Tablet PCs
Portable Devices
Near Field Communication (NFC) Capable
SIM Card Power Supply
Description
The FPF1320/21 is a Dual-Input Single-Output (DISO)
load switch consisting of two sets of slew-rate
controlled, low on-resistance, P-channel MOSFET
switches and integrated analog features. The slew-rate-
controlled turn-on characteristic prevents inrush current
and the resulting excessive voltage droop on the power
rails. The input voltage range operates from 1.5 V to
5.5 V to align with the requirements of low-voltage
portable device power rails. FPF1320/21 performs
seamless power-source transitions between two input
power rails using the SEL pin with advanced break-
before-make operation.
FPF1320/21 has a TRCB function to block unwanted
reverse current from output to input during ON/OFF
states. The switch is controlled by logic inputs of the
SEL and EN pins, which are capable of interfacing
directly with low-voltage control signals (GPIO).
FPF1321 has 65 on-chip load resistor for output quick
discharge when EN is LOW.
FPF1320/21 is available in 1.0 mm x 1.5 mm WLCSP,
6-bump, with 0.5 mm pitch. FPF1321B is available in
1.0 mm x 1.5 mm WLCSP, 6-bump, 0.5 mm pitch with
backside laminate.
Ordering Information
Part Number
Top
Mark
Switch Per
Channel Channel (Typ.)
at 3.3 VIN
Reverse
Current
Blocking
Output Rise
Discharge Time (tR)
Package
FPF1320UCX QS DISO
FPF1321UCX QT DISO
50 m
50 m
Yes NA 130 µs 1.0 mm X 1.5 mm
Wafer-Level Chip-
Scale Package
Yes
65
130 µs
(WLCSP) 6-Bumps,
0.5 mm Pitch
FPF1321BUCX QT DISO
50 m
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
1.0 mm X 1.5 mm
Wafer-Level Chip-
Yes
65
130 µs
Scale Package
(WLCSP) 6-Bumps,
0.5 mm Pitch with
Backside Laminate
www.fairchildsemi.com


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Application Diagram
Block Diagram
Figure 1. Typical Application
Figure 2. Functional Block Diagram (Output Discharge Path for FPF1321 Only)
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
2
www.fairchildsemi.com


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Pin Configuration
Figure 3. Pin Configuration in Package View with Pin 1 Indicator
EN
A1
SEL
B1
GND
C1
VIN A
A2
VOUT
B2
VIN B
C2
VIN A
A2
VOUT
B2
VIN B
C2
EN
A1
SEL
B1
GND
C1
Pin Description
Pin #
A1
Name
EN
B1 SEL
A2 VINA
B2 VOUT
C1 GND
C2 VINB
Top View
Bottom View
Figure 4. Pin Assignments
Description
Enable input. Active HIGH. There is an internal pull-down resistor at the EN pin.
Input power selection inputs. See Table 1. There are internal pull-down resistors at the
SEL pins.
Supply Input. Input to the power switch A.
Switch output
Ground
Supply Input. Input to power switch B.
Table 1.
SEL
LOW
HIGH
Truth Table
EN Switch A
HIGH
ON
HIGH
OFF
X LOW
OFF
Switch B
OFF
ON
OFF
VOUT
VINA
VINB
Floating for FPF1320
GND for FPF1321
Status
VINA Selected
VINB Selected
Both Switches are OFF
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
3
www.fairchildsemi.com


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Absolute Maximum Ratings
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameters
VIN
ISW
PD
TSTG
VINA, VINB, VSEL, VEN, VOUT to GND
Maximum Continuous Switch Current per Channel
Total Power Dissipation at TA=25°C
Operating and Storage Junction Temperature
ΘJA
Thermal Resistance, Junction-to-Ambient
(1 in.2 Pad of 2-oz. Copper)
Human Body Model, JESD22-A114
ESD
Electrostatic Discharge
Capability
Charged Device Model, JESD22-C101
Air Discharge (VINA, VINB to GND),
IEC61000-4-2 System Level
Contact Discharge (VINA, VINB to
GND), IEC61000-4-2 System Level
Notes:
1. Measured using 2S2P JEDEC std. PCB.
2. Measured using 2S2P JEDEC PCB cold-plate method.
Min.
-0.3
-65
6.0
1.5
15.0
8.0
Max.
6
1.5
1.2
150
85(1)
110(2)
Unit
V
A
W
°C
°C/W
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VIN
TA
Parameters
Input Voltage on VINA, VINB
Ambient Operating Temperature
Min.
1.5
-40
Max.
5.5
85
Unit
V
°C
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
4
www.fairchildsemi.com


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Electrical Characteristics
VINA=VINB=1.5 to 5.5 V, TA=-40 to 85°C unless otherwise noted. Typical values are at VINA=VINB=3.3 V and TA=25°C.
Symbol
Parameters
Condition
Basic Operation
VINA, VINB
ISD
Input Voltage
Shutdown Current
IQ Quiescent Current
RON On-Resistance
VIH
SEL, EN Input Logic High
Voltage
SEL=HIGH or LOW, EN=GND,
VOUT=GND, VINA=VINB=5.5 V
IOUT=0mA, SEL=HIGH or LOW,
EN=HIGH, VINA=VINB=5.5 V
VINA=VINB=5.5 V, IOUT=200 mA,
TA=25°C
VINA=VINB=3.3 V, IOUT=200 mA,
TA=25°C
VINA=VINB=1.8 V, IOUT=200 mA,
TA=25°C to 85°C
VINA=VINB=1.5 V, IOUT=200 mA,
TA=25°C
VINA, VINB=1.5 V – 5.5 V
SEL, EN Input Logic Low
Voltage
VINA, VINB=1.8 V – 5.5 V
VIL
SEL, EN Input Logic Low
Voltage
VINA, VINB=1.5 V – 1.8 V
VDROOP_OUT
Output Voltage Droop while
Channel Switching from
Higher Input Voltage Lower
Input Voltage(3)
VINA=3.3 V, VINB=5 V, Switching from
VINA VINB, RL=150 , COUT=1 µF
ISEL/IEN
Input Leakage at SEL and
EN Pin
RSEL_PD/REN_PD
Pull-Down Resistance at
SEL or EN Pin
RPD
Output Pull-Down
Resistance
True Reverse Current Blocking
SEL=HIGH or LOW, EN=GND,
IFORCE=20 mA, TA=25°C, FPF1321
VT_RCB
VR_RCB
RCB Protection Trip Point
RCB Protection Release
Trip Point
VOUT - VINA or VINB
VINA or VINB -VOUT
IRCB
VINA or VINB Current During VOUT=5.5 V, VINA or VINB=Short to
RCB
GND
tRCB_ON
RCB Response Time when
Device is ON(3)
VINA or VINB=5 V, VOUTVINA,B=100 mV
Min. Typ. Max. Unit
1.5 5.5 V
5 µA
12 22 μA
42 60
50
m
80
170
1.15 V
0.65 V
0.60
100 mV
1.2 μA
7 M
65
45 mV
25 mV
9 15 μA
5 µs
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
5
www.fairchildsemi.com


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Electrical Characteristics (Continued)
VINA=VINB=1.5 to 5.5 V, TA=-40 to 85°C unless otherwise noted. Typical values are at VINA=VINB=3.3 V and TA=25°C.
Symbol
Parameters
Condition
Min.
Dynamic Characteristics
tDON
tR
tON
tDOFF
tF
tOFF
tDOFF
tF
tOFF
Turn-On Delay(4)
VOUT Rise Time(4)
Turn-On Time(6)
Turn-Off Delay(4)
VOUT Fall Time(4)
Turn-Off Time(7)
Turn-Off Delay(4,5)
VOUT Fall Time(4,5)
Turn-Off Time(5,7)
VINA or VINB=3.3 V, RL=150 ,
CL=1 µF, TA=25°C, SEL: HIGH,
EN: LOW HIGH
VINA or VINB=3.3 V, RL=150 ,
CL=1 µF, TA=25°C, SEL: HIGH,
EN: HIGH LOW
VINA or VINB =3.3 V, RL=150 ,
CL=1 µF, TA=25°C, SEL: HIGH,
EN: HIGH LOW,
Output Discharge Mode, FPF1321
tTRANR
tSLH
Transition Time
LOW HIGH(4)
Switch-Over Rising Delay(4)
VINA=3.3 V, VINB=5 V,
Switching from VINA VINB,
SEL: LOW HIGH, EN: HIGH,
RL=150 , CL=1 µF, TA=25°C
tTRANF
tSHL
Transition Time
HIGH LOW(4)
Switch-Over Falling Delay(4)
VINA=3.3 V, VINB=5 V,
Switching from VINB VINA,
SEL: HIGH LOW, EN: HIGH,
RL=150 , C=1 µF, TA=25°C
Notes:
3. This parameter is guaranteed by design and characterization; not production tested.
4. tDON/tDOFF/tR/tF/tTRANR/tTRANF/tSLH/tSHL are defined in Figure 5.
5. FPF1321 output discharge is enabled during off.
6. tON=tR + tDON.
7. tOFF=tF + tDOFF.
Typ. Max. Unit
120 μs
130 μs
250 μs
15 μs
320 μs
335 μs
6 μs
110 μs
116 μs
3 μs
1 μs
45 μs
5 μs
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
6
www.fairchildsemi.com


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Timing Diagram
Figure 5. Dynamic Behavior Timing Diagram
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
7
www.fairchildsemi.com


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Typical Characteristics
Figure 6. Supply Current vs. Temperature
Figure 7. Supply Current vs. Supply Voltage
Figure 8. Shutdown Current vs. Temperature
Figure 9. Shutdown Current vs. Supply Voltage
Figure 10. RON vs. Temperature
Figure 11. RON vs. Supply Voltage
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
8
www.fairchildsemi.com


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Typical Characteristics
Figure 12. VIL vs. Temperature
Figure 13. VIL vs. Supply Voltage
Figure 14. VIH vs. Temperature
Figure 15. VIH vs. Supply Voltage
Figure 16. VIH / VIL vs. Supply Voltage
Figure 17. RSEL_PD and REN_PD vs. Temperature
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
9
www.fairchildsemi.com


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Typical Characteristics
Figure 18. RSEL_PD and REN_PD vs. Supply Voltage
Figure 19. tDON and tDOFF vs. Temperature
Figure 20. tR and tF with FPF1320 vs. Temperature Figure 21. tR and tF with FPF1321 vs. Temperature
Figure 22. Transition Time vs. Temperature
Figure 23. Switch Over Time vs. Temperature
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
10
www.fairchildsemi.com


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Typical Characteristics
Figure 24. TRCB Trip and Release vs. Temperature
Figure 25. IRCB vs. Temperature
Figure 26. RPD with FPF1321 vs. Temperature
Figure 27. Turn-On Response
(VINA=3.3 V, CIN=1 µF, COUT=1 µF, RL=150 ,
SEL=LOW)
Figure 28. Turn-Off Response with FPF1320
(VINA=3.3 V, CIN=1 µF, COUT=1 µF, RL=150 ,
SEL=LOW)
Figure 29. Turn-Off Response with FPF1321
(VINA=3.3 V, CIN=1 µF, COUT=1 µF, RL=150 ,
SEL=LOW)
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
11
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Typical Characteristics
Figure 30. Power Source Transition from 3.3 V to 5 V Figure 31. Power Source Transition from 5 V to 3.3 V
(VINA=3.3 V, VINB=5 V, CIN=1 µF, COUT=1 µF,
(VINA=3.3 V, VINB=5 V, CIN=1 µF, COUT=1 µF,
RL=150 )
RL=150 )
Figure 32. TRCB During Off (VINA=VINB=Floating,
VOUT=5V, CIN=1 µF, COUT=1 µF, EN=LOW, No RL)
Figure 33. TRCB During On (VINA=5 V, VOUT=6 V,
CIN=1 µF, COUT=1 µF, EN=HIGH, No RL)
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
12
www.fairchildsemi.com


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Operation and Application Description
The FPF1320 and FPF1321 are dual-input single-output
power multiplexer switches with controlled turn-on and
seamless power source transition. The core is a 50 m
P-channel MOSFET and controller capable of
functioning over a wide input operating range of 1.5 V to
5.5 V per channel. The EN and SEL pins are active-
HIGH, GPIO/CMOS-compatible input. They control the
state of the switch and input power source selection,
respectively. TRCB functionality blocks unwanted
reverse current during both ON and OFF states when
higher VOUT than VINA or VINB is applied. FPF1321 has a
65 output discharge path during off.
Input Capacitor
To limit the voltage drop on the input supply caused by
transient inrush current when the switch turns on into a
discharged load capacitor; a capacitor must be placed
between the VINA or VINB pins to the GND pin. At least
1 µF ceramic capacitor, CIN, placed close to the pins, is
usually sufficient. Higher-value CIN can be used to
reduce more the voltage drop.
Inrush Current
Inrush current occurs when the device is turned on.
Inrush current is dependent on output capacitance and
slew rate control capability, as expressed by:
I INRUSH
= COUT
× VIN
VINITIAL
tR
+ I LOAD
where:
(1)
COUT: Output capacitance;
tR: Slew rate or rise time at VOUT;
VIN: Input voltage, VINA or VINB;
VINITIAL: Initial voltage at COUT, usually GND; and
ILOAD: Load current.
Higher inrush current causes higher input voltage drop,
depending on the distributed input resistance and input
capacitance. High inrush current can cause problems.
FPF1320/1 has a 130 µs of slew rate capability under
3.3 VIN at 1 µF of COUT and 150 of RL so inrush
current and input voltage drop can be minimized.
Power Source Selection
Input power source selection can be controlled by the
SEL pin. When SEL is LOW, output is powered from
VINA while SEL is HIGH, VINB is powering output. The
SEL signal is ignored during device OFF.
Output Voltage Drop during Transition
Output voltage drop usually occurs during input power
source transition period from low voltage to high
voltage. The drop is highly dependent on output
capacitance and load current.
FPF1320/1 adopts an advanced break-before-make
control, which can result in minimized output voltage
drop during the transition time.
Output Capacitor
Capacitor COUT of at least 1 µF is highly recommended
between the VOUT and GND pins to achieve minimized
output voltage drop during input power source transition.
This capacitor also prevents parasitic board inductance.
True Reverse-Current Blocking
The true reverse-current blocking feature protects the
input source against current flow from output to input
regardless of whether the load switch is on or off.
Board Layout
For best performance, all traces should be as short as
possible. To be most effective, the input and output
capacitors should be placed close to the device to
minimize the effect that parasitic trace inductance on
normal and short-circuit operation. Wide traces or large
copper planes for power pins (VINA, VINB, VOUT and
GND) minimize the parasitic electrical effects and the
thermal impedance.
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
13
www.fairchildsemi.com


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Physical Dimensions
0.03 C
2X
E AF
B
BALL A1
INDEX AREA
D
TOP VIEW
0.03 C
2X
0.05 C
0.06 C
0.625
0.539
E
(Ø0.350)
SOLDER MASK
OPENING
A1
(Ø0.250)
Cu Pad
(1.00)
(0.50)
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
0.332±0.018
0.250±0.025
C SEATING PLANE D
SIDE VIEWS
0.50
0.005 C A B
Ø0.315 +/- .025
6X
1.00
0.50
12
C
B (Y) ±0.018
A
F
(X) ±0.018
BOTTOM VIEW
NOTES:
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCE
PER ASMEY14.5M, 1994.
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
E. PACKAGE NOMINAL HEIGHT IS 582 MICRONS
±43 MICRONS (539-625 MICRONS).
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
G. DRAWING FILNAME: MKT-UC006AFrev2.
Figure 34. 6-Ball, 1.0 x 1.5 mm, Wafer-Level Chip-Scale Package (WLCSP)
Product-Specific Dimensions
Product
FPF1320UCX
FPF1321UCX
FPF1321BUCX
D
1460 µm ±30 µm
1460 µm ±30 µm
1460 µm ±30 µm
E
960 µm ±30 µm
960 µm ±30 µm
960 µm ±30 µm
X
230 µm
230 µm
230 µm
Y
230 µm
230 µm
230 µm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
http://www.fairchildsemi.com/dwg/UC/UC006AF.pdf
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
14
www.fairchildsemi.com


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© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
15
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