Operation and Application Description
The FPF1048 is a low-RON P-channel load switch with
controlled turn-on and True Reverse Current Blocking
(TRCB). The core is a 23 mΩ P-channel MOSFET and
controller capable of functioning over a wide input
operating range of 1.5 to 5.5 V. The ON pin, an active-
HIGH, GPIO/CMOS-compatible input; controls the state
of the switch. TRCB functionality blocks unwanted
reverse current during both ON and OFF states when
higher VOUT than VIN is applied.
To limit the voltage drop on the input supply caused by
transient inrush current when the switch turns on into a
discharged load capacitor; a capacitor must be placed
between the VIN and GND pins. At least 1 µF ceramic
capacitor, CIN, placed close to the pins is usually
sufficient. Higher-value CIN can be used to reduce the
voltage drop in higher-current applications.
Inrush current occurs when the device is turned on.
Inrush current is dependent on output capacitance and
slew rate control capability, as expressed by:
COUT: Output capacitance;
tR: Slew rate or rise time at VOUT;
VIN: Input voltage;
VINITIAL: Initial voltage at COUT, usually GND; and
ILOAD: Load current.
Higher inrush current causes higher input voltage drop,
depending on the distributed input resistance and input
capacitance. High inrush current can cause problems.
FPF1048 has a 2.7 ms of slew rate capability under
4.5 VIN at 1000 µF of COUT and 5 Ω of RL so inrush
current can be minimized and no input voltage drop
appears. Table 1 and Figure 28 show the values and
actual waveforms with CIN=10 µF, COUT=100 µF, and no
Table 1. Inrush Current by Input Voltage
Inrush Current [mA]
with 2.7 ms tR
Figure 28. Inrush Current Waveform, Under 5 VIN,
COUT=100 μF, no Load
At least 0.1 µF capacitor, COUT, should be placed
between the VOUT and GND pins. This capacitor
prevents parasitic board inductance from forcing VOUT
below GND when the switch is on.
True Reverse Current Blocking
The true reverse current blocking feature protects the
input source against current flow from output to input
regardless of whether the load switch is on or off.
For best performance, all traces should be as short as
possible. To be most effective, the input and output
capacitors should be placed close to the device to
minimize the effect that parasitic trace inductance on
normal and short-circuit operation. Using wide traces or
large copper planes for all pins (VIN, VOUT, ON, and
GND) minimizes the parasitic electrical effects and the
case-to-ambient thermal impedance.
© 2011 Fairchild Semiconductor Corporation
FPF1048 • Rev. 1.8