FDML7610S Datasheet PDF
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FDML7610S
PowerTrench® Power Stage
Asymmetric Dual N-Channel MOSFET
Features
Q1: N-Channel
„ Max rDS(on) = 7.5 mΩ at VGS = 10 V, ID = 12 A
„ Max rDS(on) = 12 mΩ at VGS = 4.5 V, ID = 10 A
Q2: N-Channel
„ Max rDS(on) = 4.2 mΩ at VGS = 10 V, ID = 17 A
„ Max rDS(on) = 5.5 mΩ at VGS = 4.5 V, ID = 14 A
„ RoHS Compliant
April 2013
General Description
This device includes two specialized N-Channel MOSFETs in a
dual MLP package.The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
efficiency.
Applications
„ Computing
„ Communications
„ General Purpose Point of Load
„ Notebook VCORE
Pin 1
D1 D1 D1
G1
D1
PHASE
(S1/D2)
S2 5
S2 6
Q2
PHASE
4 D1
3 D1
G2S2 S2S2
S2 7
G2 8
2 D1
Q1 1 G1
Top
MLP 3X4.5
Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
PD
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
Power Dissipation for Single Operation
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 3)
TC = 25 °C
TC = 25 °C
TA = 25 °C
TA = 25 °C
TA = 25 °C
Q1 Q2
30 30
±20 ±20
30 28
40
121a
60
171b
40
2.11a
0.81c
40
2.21b
0.91d
-55 to +150
Units
V
V
A
W
°C
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
601a
1501c
4
561b
1401d
3.5
°C/W
Device Marking
FDML7610S
Device
FDML7610S
Package
MLP3X4.5
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
1
www.fairchildsemi.com


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Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
IDSS
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
IGSS
Gate to Source Leakage Current
VGS = 20 V, VDS= 0 V
Type Min
Q1 30
Q2 30
Q1
Q2
Q1
Q2
Q1
Q2
Typ
15
14
Max Units
V
mV/°C
1 μA
500 μA
100 nA
100 nA
On Characteristics
VGS(th)
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
rDS(on)
Drain to Source On Resistance
gFS Forward Transconductance
Dynamic Characteristics
Ciss Input Capacitance
Coss
Output Capacitance
Crss Reverse Transfer Capacitance
Rg Gate Resistance
VGS = VDS, ID = 250 μA
VGS = VDS, ID = 1 mA
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
VGS = 10 V, ID = 12 A
VGS = 4.5 V, ID = 10 A
VGS = 10 V, ID = 12 A , TJ = 125 °C
VGS = 10 V, ID = 17 A
VGS = 4.5 V, ID = 14 A
VGS = 10 V, ID = 17 A , TJ = 125 °C
VDS = 5 V, ID = 12 A
VDS = 5 V, ID = 17 A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
1
1
1.8 3
1.8 3
V
-6
-5
mV/°C
6.0 7.5
8.5 12
8.3 12
mΩ
3.2 4.2
4.1 5.5
4.1 6
63
86
S
Q1:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q2:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
1315
2960
455
1135
45
100
0.9
0.6
1750
3940
600
1510
70
150
pF
pF
pF
Ω
Switching Characteristics
td(on)
Turn-On Delay Time
tr Rise Time
td(off)
Turn-Off Delay Time
tf Fall Time
Qg Total Gate Charge
Qg Total Gate Charge
Qgs Gate to Source Gate Charge
Qgd Gate to Drain “Miller” Charge
Q1:
VDD = 15 V, ID = 12 A,
VGS = 10 V, RGEN = 6 Ω
Q2:
VDD = 15 V, ID = 17 A,
VGS = 10 V, RGEN = 6 Ω
VGS = 0 V to 10 V Q1
VDD = 15 V,
VGS = 0 V to 4.5 V ID = 12 A
Q2
VDD = 15 V,
ID = 17A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
8.6
13
18
23
ns
2.5
4
10
10
ns
20
31
32
49
ns
2.3
3.1
10
10
ns
20
43
28
60
nC
9.3
20
13
28
nC
4.3
8.9
nC
2.2
4.7
nC
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
2
www.fairchildsemi.com


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Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type Min Typ Max Units
Drain-Source Diode Characteristics
VSD
Source to Drain Diode
Forward Voltage
VGS = 0 V, IS = 12 A
VGS = 0 V, IS = 17 A
(Note 2)
(Note 2)
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
Q1
IF = 12 A, di/dt = 100 A/μs
Q2
IF = 17 A, di/dt = 300 A/μs
Q1
Q2
Q1
Q2
Q1
Q2
0.8 1.2
0.8 1.2
27 43
35 56
10 18
40 64
V
ns
nC
Notes:
1: RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined
by the user's board design.
a. 60 °C/W when mounted on
a 1 in2 pad of 2 oz copper
b. 56 °C/W when mounted on
a 1 in2 pad of 2 oz copper
c. 150 °C/W when mounted on a
minimum pad of 2 oz copper
d. 140 °C/W when mounted on a
minimum pad of 2 oz copper
2: Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
3
www.fairchildsemi.com


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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
40
VGS = 10 V
VGS = 6 V
30
VGS = 4.5 V
VGS = 4 V
20
4
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
3
VGS = 3.5 V
VGS = 4 V
2
VGS = 4.5 V
10
0
0.0
VGS = 3.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0.5 1.0 1.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
2.0
Figure 1. On Region Characteristics
1
VGS = 6 V VGS = 10 V
0
0 10 20 30 40
ID, DRAIN CURRENT (A)
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
1.6
ID = 12 A
VGS = 10 V
1.4
40
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
30
ID = 12 A
1.2
1.0
0.8
-75 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. Normalized On Resistance
vs Junction Temperature
20
TJ = 125 oC
10
TJ = 25 oC
0
2468
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 4. On-Resistance vs Gate to
Source Voltage
10
40
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
30
VDS = 5 V
TJ = 150 oC
20
TJ = 25 oC
10
TJ = -55 oC
0
1.5 2.0 2.5 3.0 3.5 4.0
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
40
VGS = 0 V
10
1 TJ = 150 oC
0.1
TJ = 25 oC
0.01
TJ = -55 oC
0.001
0.0
0.2 0.4 0.6 0.8 1.0
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
1.2
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
4
www.fairchildsemi.com


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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
10
ID = 12 A
8
6
4
2
VDD = 10 V
VDD = 15 V
VDD = 20 V
0
0 5 10 15 20
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
2000
1000
Ciss
Coss
100
f = 1 MHz
Crss
VGS = 0 V
10
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure8. Capacitance vsDrain
to Source Voltage
60
VGS = 10 V
40
VGS = 4.5 V
20 Limited by Package
RθJC = 4 oC/W
0
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
Figure 9. Maximum Continuous Drain Current vs
Case Temperature
1000
100
100
100us
10
1 ms
1
THIS AREA IS
LIMITED BY rDS(on)
10 ms
100 ms
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 150 oC/W
TA = 25 oC
0.01
0.01 0.1
1
1s
10s
DC
10 100 200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 10. Forward Bias Safe Operating Area
SINGLE PULSE
RθJA = 150 oC/W
TA = 25 oC
10
1
0.5
10-4
10-3
10-2
10-1
1
t, PULSE WIDTH (s)
10
Figure 11. Single Pulse Maximum Power Dissipation
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
5
100 1000
www.fairchildsemi.com


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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.1 0.05
0.02
0.01
PDM
0.01
0.001
10-4
SINGLE PULSE
RθJA = 150 oC/W
(Note 1c)
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
10-3
10-2
10-1
1
10
t, RECTANGULAR PULSE DURATION (sec)
100
Figure 12. Junction-to-Ambient Transient Thermal Response Curve
1000
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
6
www.fairchildsemi.com


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Typical Characteristics (Q2 N-Channel) TJ = 25 oC unlenss otherwise noted
40
VGS = 10 V
30
VGS = 4.5 V
VGS = 4 V
20
VGS = 3.5 V
10
0
0.0
VGS = 3 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0.2 0.4 0.6
VDS, DRAIN TO SOURCE VOLTAGE (V)
0.8
Figure 13. On-Region Characteristics
6
PULSE DURATION = 80 μs
5 DUTY CYCLE = 0.5% MAX
VGS = 3 V
4
3
VGS = 3.5 V
2
1
VGS = 4 V
VGS = 4.5 V VGS = 10 V
0
0 10 20 30 40
ID, DRAIN CURRENT (A)
Figure 14. Normalized on-Resistance vs Drain
Current and Gate Voltage
1.6
ID = 17 A
VGS = 10 V
1.4
1.2
1.0
0.8
0.6
-75 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 15. Normalized On-Resistance
vs Junction Temperature
20
ID = 17 A
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
15
10
TJ = 125 oC
5
TJ = 25 oC
0
2468
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 16. On-Resistance vs Gate to
Source Voltage
10
40
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
30 VDS = 5 V
TJ = 125 oC
20
TJ = 25 oC
10
TJ = -55 oC
0
1.5 2.0 2.5 3.0 3.5
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 17. Transfer Characteristics
40
VGS = 0 V
10
TJ = 125 oC
1
TJ = 25 oC
0.1
TJ = -55 oC
0.01
0.0
0.2 0.4 0.6 0.8 1.0
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 18. Source to Drain Diode
Forward Voltage vs Source Current
1.2
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
7
www.fairchildsemi.com


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Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
10
ID = 17A
8
6
4
2
VDD = 10 V
VDD = 15 V
VDD = 20 V
0
0 10 20 30 40 50
Qg, GATE CHARGE (nC)
Figure 19. Gate Charge Characteristics
5000
1000
Ciss
Coss
100 f = 1 MHz
VGS = 0 V
60
0.1
1
Crss
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 20. Capacitance vs Drain
to Source Voltage
30
80
VGS = 10 V
60
VGS = 4.5 V
40
RθJC = 3.5 oC/W
20
Limited by package
0
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
Figure 21. Maximun Continuous Drain
Current vs Case Temperature
300
100
100
10
1 ms
1 THIS AREA IS
LIMITED BY rDS(on)
10 ms
100 ms
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 140 oC/W
TA = 25 oC
0.01
0.01 0.1
1
1s
10s
DC
10 100 200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 22. Forward Bias Safe
Operating Area
SINGLE PULSE
RθJA = 140 oC/W
TA = 25 oC
10
1
0.001
0.01
0.1 1
t, PULSE WIDTH (sec)
10
Figure 23. Single Pulse Maximum Power Dissipation
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
8
100
1000
www.fairchildsemi.com


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Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.1 0.05
0.02
0.01
PDM
0.01
0.001
10-3
SINGLE PULSE
RθJA = 140 oC/W
Note 1d
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
10-2
10-1
1
10
t, RECTANGULAR PULSE DURATION (sec)
100
Figure24. Junction-to-Ambient Transient Thermal Response Curve
1000
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
9
www.fairchildsemi.com


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Typical Characteristics (continued)
SyncFETTM Schottky body diode
Characteristics
Fairchild’s SyncFETTM process embeds a Schottky diode in
parallel with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
with a MOSFET. Figure 25 shows the reverse recovery
characteristic of the FDML7610S.
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
20
15
di/dt = 300 A/μs
10
5
0
-5
0 50 100 150 200 250
TIME (ns)
Figure 25. FDML7610S SyncFETTM body
diode reverse recovery characteristic
10000
1000
100
TJ = 125 oC
TJ = 100 oC
10
TJ = 25 oC
1
0 5 10 15 20 25 30
VDS, REVERSE VOLTAGE (V)
Figure 26. SyncFETTM body diode reverse
leakage versus drain-source voltage
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
10
www.fairchildsemi.com


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Application Information
1. Switch Node Ringing Suppression
Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch
node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage
solution rings significantly less than competitor solutions under the same set of test conditions.
Power Stage Device
Competitors solution
Figure 29. Power Stage phase node rising edge, High Side Turn on
*Patent Pending
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
11
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Figure 30. Shows the Power Stage in a buck converter topology
2. Recommended PCB Layout Guidelines
As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power
train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2),
should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout proce-
dure is discussed below to maximize the electrical and thermal performance of the part.
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
Figure 31. Recommended PCB Layout
12
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Following is a guideline, not a requirement which the PCB designer should consider:
1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic
inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close
to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected
depending upon the application.
2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output
inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to
present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction
losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high
noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance
between the thermal and electrical performance of Power Stage.
3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace
resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be
directly in line (as shown in figure 31) with the inductor for space savings and compactness.
4. The PowerTrench® Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the
part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If
the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen
the high-frequency ringing.
5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side
gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the
MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate
current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses.
Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This
provides a very compact path for the drive signals and improves efficiency of the part.
6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise
transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET.
7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction.
Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as
ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected
from the backside via a network of low inductance vias.
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
13
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