Fairchild Semiconductor Electronic Components Datasheet



FDMS3604AS

MOSFET


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FDMS3604AS
PowerTrench® Power Stage
September 2011
30 V Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
„ Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A
„ Max rDS(on) = 11 mΩ at VGS = 4.5 V, ID = 11 A
Q2: N-Channel
„ Max rDS(on) = 2.6 mΩ at VGS = 10 V, ID = 23 A
„ Max rDS(on) = 3.5 mΩ at VGS = 4.5 V, ID = 21 A
„ Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
„ MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
„ RoHS Compliant
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Applications
„ Computing
„ Communications
„ General Purpose Point of Load
„ Notebook VCORE
„ Sever
G1 D1 D1 D1
D1
PHASE
(S1/D2)
G2S2
S2 S2
Top
Power 56
Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
S2 5
S2 6
S2 7
G2 8
Q2 4 D1
PHASE
3 D1
2 D1
Q1 1 G1
(Note 3)
TC = 25 °C
TC = 25 °C
TA = 25 °C
TA = 25 °C
TA = 25 °C
Q1 Q2
30 30
±20 ±20
30 40
60
131a
130
231b
40
404
2.21a
1.01c
100
1125
2.51b
1.01d
-55 to +150
Units
V
V
A
mJ
W
°C
571a
1251c
3.5
501b
1201d
2
°C/W
Device Marking
22CA
N7CC
Device
FDMS3604AS
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
Package
Power 56
1
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com


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Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
IDSS
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
IGSS
Gate to Source Leakage Current,
Forwad
VGS = 20 V, VDS= 0 V
Type Min
Q1 30
Q2 30
Q1
Q2
Q1
Q2
Q1
Q2
Typ
15
12
Max Units
V
mV/°C
1 μA
500 μA
100 nA
100 nA
On Characteristics
VGS(th)
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
rDS(on)
Drain to Source On Resistance
gFS Forward Transconductance
Dynamic Characteristics
Ciss Input Capacitance
Coss
Output Capacitance
Crss Reverse Transfer Capacitance
Rg Gate Resistance
VGS = VDS, ID = 250 μA
VGS = VDS, ID = 1 mA
Q1 1.1
2
Q2 1.1 1.8
2.7
3
V
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
-6
-5
mV/°C
VGS = 10 V, ID = 13 A
VGS = 4.5 V, ID = 11 A
VGS = 10 V, ID = 13 A , TJ = 125 °C
VGS = 10 V, ID = 23 A
VGS = 4.5 V, ID = 21 A
VGS = 10 V, ID = 23 A , TJ = 125 °C
Q1
Q2
5.8 8
8.5 11
7.8 10.8
mΩ
2 2.6
2.6 3.5
2.6 4
VDS = 5 V, ID = 13 A
VDS = 5 V, ID = 23 A
Q1 61
Q2 130
S
Q1:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q2:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
Q1
Q2
Q1
Q2
1273
3078
461
1169
50
98
1695
4095
615
1555
75
150
pF
pF
pF
Q1 0.2 0.6
Q2 0.2 0.8
2
3
Ω
Switching Characteristics
td(on)
Turn-On Delay Time
tr Rise Time
td(off)
Turn-Off Delay Time
tf Fall Time
Qg Total Gate Charge
Qg Total Gate Charge
Qgs Gate to Source Gate Charge
Qgd Gate to Drain “Miller” Charge
Q1:
VDD = 15 V, ID = 13 A, RGEN = 6 Ω
Q2:
VDD = 15 V, ID = 23 A, RGEN = 6 Ω
VGS = 0 V to 10 V Q1
VDD = 15 V,
VGS = 0 V to 4.5 V ID = 13 A
Q2
VDD = 15 V,
ID = 23 A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
8.2
13
16
23
ns
2.5
4.8
10
10
ns
20
31
32
50
ns
2.2
3.4
10
10
ns
21
47
29
66
nC
10
22
14
31
nC
3.9
9
nC
3.1
5.5
nC
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
2
www.fairchildsemi.com


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Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type Min Typ Max Units
Drain-Source Diode Characteristics
VSD
Source to Drain Diode
Forward Voltage
VGS = 0 V, IS = 13 A
VGS = 0 V, IS = 23A
(Note 2)
(Note 2)
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
Q1
IF = 13 A, di/dt = 100 A/μs
Q2
IF = 23 A, di/dt = 300 A/μs
Q1
Q2
Q1
Q2
Q1
Q2
0.8 1.2
0.8 1.2
25 40
32 51
9 18
39 62
V
ns
nC
Notes:
1: RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined
by the user's board design.
a. 57 °C/W when mounted on
a 1 in2 pad of 2 oz copper
b. 50 °C/W when mounted on
a 1 in2 pad of 2 oz copper
c. 125 °C/W when mounted on a
minimum pad of 2 oz copper
d. 120 °C/W when mounted on a
minimum pad of 2 oz copper
2: Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
4: EAS of 40 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 9 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 14 A.
5: EAS of 112 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 15 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 22 A.
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
3
www.fairchildsemi.com


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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
40
VGS = 10 V
VGS = 6 V
30
VGS = 4.5 V
VGS = 4 V
20
10
0
0.0
VGS = 3.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0.2 0.4 0.6 0.8
VDS, DRAIN TO SOURCE VOLTAGE (V)
1.0
Figure 1. On Region Characteristics
4
VGS = 3.5 V
3
2
1
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 4 V
VGS = 4.5 V
VGS = 6 V
VGS = 10 V
0
0 10 20 30
ID, DRAIN CURRENT (A)
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
40
1.6
ID = 13 A
VGS = 10 V
1.4
1.2
1.0
20
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
16
ID = 13 A
12
TJ = 125 oC
8
0.8
0.6
-75 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. Normalized On Resistance
vs Junction Temperature
4
TJ = 25 oC
0
2468
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 4. On-Resistance vs Gate to
Source Voltage
10
40
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
30
VDS = 5 V
20
TJ = 150 oC
TJ = 25 oC
10
TJ = -55 oC
0
1.5 2.0 2.5 3.0 3.5 4.0
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
40
VGS = 0 V
10
1
TJ = 150 oC
0.1
TJ = 25 oC
0.01
TJ = -55 oC
0.001
0.0
0.2 0.4 0.6 0.8 1.0
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
1.2
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
4
www.fairchildsemi.com


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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
10
ID = 13 A
8
6
4
VDD = 10 V
VDD = 15 V
VDD = 20 V
2000
1000
100
Ciss
Coss
2
0
0 5 10 15 20 25
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Crss
f = 1 MHz
VGS = 0 V
10
0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure8. Capacitance vsDrain
to Source Voltage
20
10
TJ = 25 oC
TJ = 100 oC
1
0.01
TJ = 125 oC
0.1 1 10
tAV, TIME IN AVALANCHE (ms)
Figure9. UnclampedInductive
Switching Capability
100
100
100us
10
1 ms
1
THIS AREA IS
LIMITED BY rDS(on)
10 ms
100 ms
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 125 oC/W
TA = 25 oC
0.01
0.01 0.1
1
1s
10s
DC
10 100 200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
5
100
80
60
VGS = 4.5 V
40
RθJC = 3.5 oC/W
VGS = 10 V
20
Limited by Package
0
25 50 75 100 125
TC, CASE TEMPERATURE (oC)
150
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
1000
100
10
SINGLE PULSE
RθJA = 125 oC/W
TA = 25 oC
1
0.1
10-4 10-3 10-2 10-1
1
10
t, PULSE WIDTH (sec)
100 1000
Figure 12. Single Pulse Maximum
Power Dissipation
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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
PDM
0.01
0.001
10-4
SINGLE PULSE
RθJA = 125 oC/W
(Note 1c)
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
10-3
10-2
10-1
1
10
t, RECTANGULAR PULSE DURATION (sec)
100
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
1000
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
6
www.fairchildsemi.com


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Typical Characteristics (Q2 N-Channel) TJ = 25 oC unlenss otherwise noted
100
VGS = 10 V
VGS = 4.5 V
80
VGS = 4 V
60
40
20
0
0.0
VGS = 3.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3 V
0.2 0.4 0.6 0.8
VDS, DRAIN TO SOURCE VOLTAGE (V)
1.0
Figure 14. On-Region Characteristics
8
PULSE DURATION = 80 μs
VGS = 3 V
DUTY CYCLE = 0.5% MAX
6
VGS = 3.5 V
4
VGS = 4 V VGS = 4.5 V
2
VGS = 10 V
0
0 20 40 60 80 100
ID, DRAIN CURRENT (A)
Figure 15. Normalized on-Resistance vs Drain
Current and Gate Voltage
1.6
ID = 23 A
VGS = 10 V
1.4
1.2
1.0
0.8
-75 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 16. Normalized On-Resistance
vs Junction Temperature
12
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
9
ID = 23 A
6
TJ = 125 oC
3
TJ = 25 oC
0
2468
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 17. On-Resistance vs Gate to
Source Voltage
10
100
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
80
VDS = 5 V
60
40
20
0
1.5
TJ = 125 oC
TJ = 25 oC
TJ = -55 oC
2.0 2.5 3.0 3.5
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 18. Transfer Characteristics
4.0
100
VGS = 0 V
10 TJ = 125 oC
1
0.1
0.01
TJ = 25 oC
TJ = -55 oC
0.001
0.0
0.2 0.4 0.6 0.8 1.0
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 19. Source to Drain Diode
Forward Voltage vs Source Current
1.2
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
7
www.fairchildsemi.com


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Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
10
ID = 23 A
8
6
4
2
VDD = 10 V
VDD = 15 V
VDD = 20 V
0
0 10 20 30 40 50
Qg, GATE CHARGE (nC)
Figure 20. Gate Charge Characteristics
10000
1000
Ciss
Coss
100
Crss
f = 1 MHz
VGS = 0 V
10
0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure 21. Capacitance vs Drain
to Source Voltage
50
TJ = 25 oC
10
TJ = 100 oC
TJ = 125 oC
1
0.01
0.1 1 10 100
tAV, TIME IN AVALANCHE (ms)
Figure 22. Unclamped Inductive
Switching Capability
200
100
1000
10 1 ms
THIS AREA IS
1 LIMITED BY rDS(on)
10 ms
100 ms
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 120 oC/W
TA = 25 oC
0.01
0.01
0.1
1
1s
10s
DC
10 100200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 24. Forward Bias Safe
Operating Area
160
RθJC = 2 oC/W
120
VGS = 10 V
80
VGS = 4.5 V
40
Limited by Package
0
25 50 75 100 125
TC, CASE TEMPERATURE (oC)
150
Figure 23. Maximun Continuous Drain
Current vs Case Temperature
1000
SINGLE PULSE
100 RθJA = 120 oC/W
TA = 25 oC
10
1
0.1
10-3
10-2
10-1
1
10
t, PULSE WIDTH (sec)
100
Figure 25. Single Pulse Maximum
Power Dissipation
1000
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
8
www.fairchildsemi.com


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Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
0.1 0.02
0.01
0.01
SINGLE PULSE
RθJA = 120 oC/W
(Note 1d)
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
0.001
10-3
10-2
10-1
1
10
t, RECTANGULAR PULSE DURATION (sec)
100
Figure 26. Junction-to-Ambient Transient Thermal Response Curve
1000
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
9
www.fairchildsemi.com


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Typical Characteristics (continued)
SyncFET Schottky body diode
Characteristics
Fairchild’s SyncFET process embeds a Schottky diode in parallel
with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
with a MOSFET. Figure 27 shows the reverse recovery
characteristic of the FDMS3604AS.
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
25
20
15
10
5
0
-5
0
didt = 300 A/μs
50 100
TIME (ns)
150
200
10-2 TJ = 125 oC
10-3
TJ = 100 oC
10-4
10-5
10-6
0
TJ = 25 oC
5 10 15 20 25
VDS, REVERSE VOLTAGE (V)
30
Figure 27. FDMS3604AS SyncFET body
diode reverse recovery characteristic
Figure 28. SyncFET body diode reverse
leakage versus drain-source voltage
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
10
www.fairchildsemi.com


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Application Information
1. Switch Node Ringing Suppression
Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch
node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage
solution rings significantly less than competitor solutions under the same set of test conditions.
Power Stage Device
Competitors solution
Figure 29. Power Stage phase node rising edge, High Side Turn on
*Patent Pending
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
11
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Figure 30. Shows the Power Stage in a buck converter topology
2. Recommended PCB Layout Guidelines
As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power
train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2),
should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout proce-
dure is discussed below to maximize the electrical and thermal performance of the part.
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
Figure 31. Recommended PCB Layout
12
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Following is a guideline, not a requirement which the PCB designer should consider:
1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic
inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close
to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected
depending upon the application.
2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output
inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to
present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction
losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high
noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance
between the thermal and electrical performance of Power Stage.
3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace
resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be
directly in line (as shown in figure 31) with the inductor for space savings and compactness.
4. The PowerTrench® Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the
part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If
the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen
the high-frequency ringing.
5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side
gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the
MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate
current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses.
Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This
provides a very compact path for the drive signals and improves efficiency of the part.
6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise
transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET.
7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction.
Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as
ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected
from the backside via a network of low inductance vias.
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
13
www.fairchildsemi.com


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Dimensional Outline and Pad Layout
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
14
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TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
2Cool™
AccuPower™
Auto-SPM™
AX-CAP™*
BitSiC®
Build it Now™
CorePLUS™
CorePOWER™
CROSSVOLT
CTL™
Current Transfer Logic™
DEUXPEED®
Dual Cool™
EcoSPARK®
EfficentMax™
ESBC™
®
tm
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
FAST®
FastvCore™
FETBench™
FlashWriter® *
FPS™
F-PFS™
FRFET®
Global Power ResourceSM
Green FPS™
Green FPS™ e-Series™
Gmax
GTO™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
MicroPak™
MicroPak2™
MillerDrive™
MotionMax™
Motion-SPM™
mWSaver™
OptiHiT™
OPTOLOGIC®
OPTOPLANAR®
®
tm
PDP SPM™
Power-SPM™
PowerTrench®
PowerXS™
Programmable Active Droop™
QFET®
QS™
Quiet Series™
RapidConfigure™
Saving our world, 1mW/W/kW at a time™
SignalWise™
SmartMax™
SMART START™
SPM®
STEALTH™
SuperFET®
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SupreMOS®
SyncFET™
Sync-Lock™
®*
The Power Franchise®
The Right Technology for Your Success™
®
tm
TinyBoost™
TinyBuck™
TinyCalc™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
TranSiC®
TriFault Detect™
TRUECURRENT®*
μSerDes™
UHC®
Ultra FRFET™
UniFET™
VCX™
VisualMax™
XS™
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY
PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY
THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used here in:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body or (b) support or sustain life,
and (c) whose failure to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
ANTI-COUNTERFEITING POLICY
Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website,
www.Fairchildsemi.com, under Sales Support.
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their
parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed
application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the
proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild
Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild
Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of
up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and
warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is
committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative / In Design
Preliminary
First Production
No Identification Needed
Obsolete
Full Production
Not In Production
©2011 Fairchild Semiconductor Corporation
FDMS3604AS Rev.C4
Definition
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Rev. I55
15 www.fairchildsemi.com




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