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FDMS3669S
PowerTrench® Power Stage
Asymmetric Dual N-Channel MOSFET
Features
Q1: N-Channel
„ Max rDS(on) = 10 mΩ at VGS = 10 V, ID = 13 A
„ Max rDS(on) = 14.5 mΩ at VGS = 4.5 V, ID = 10 A
Q2: N-Channel
„ Max rDS(on) = 5 mΩ at VGS = 10 V, ID = 18 A
„ Max rDS(on) = 5.2 mΩ at VGS = 4.5 V, ID = 17 A
„ Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
„ MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
„ RoHS Compliant
January 2013
General Description
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
efficiency.
Applications
„ Computing
„ Communications
„ General Purpose Point of Load
„ Notebook VCORE
Pin 1
Pin 1
G1
D1
D1
D1
D1
PHASE
(S1/D2)
G2
S2
S2
S2
Top Power 56 Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
Thermal Characteristics
S2 5
S2 6
S2 7
G2 8
Q2 4 D1
PHASE
3 D1
2 D1
Q1 1 G1
(Note 3)
TC = 25 °C
TC = 25 °C
TA = 25 °C
(Note 6)
TA = 25 °C
TA = 25 °C
Q1 Q2
30 30
±20 ±12
24 60
43
131a
75
181b
50
614
2.21a
1.01c
60
485
2.51b
1.01d
-55 to +150
Units
V
V
A
mJ
W
°C
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
571a
1251c
5.0
501b
1201d
2.8
°C/W
Device Marking
9ACF
21CD
Device
FDMS3669S
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
Package
Power 56
1
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com


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Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type Min Typ Max Units
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
IDSS
IGSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V
Q1 30
Q2 30
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
Q1
Q2
Gate to Source Leakage Current
VGS = 20 V, VDS= 0 V
VGS = 12 V, VDS= 0 V
Q1
Q2
V
16
20
mV/°C
1 μA
500 μA
100 nA
100 nA
On Characteristics
VGS(th)
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
rDS(on)
Drain to Source On Resistance
gFS Forward Transconductance
VGS = VDS, ID = 250 μA
VGS = VDS, ID = 1 mA
Q1 1.1 2.0
Q2 1.1 1.5
2.7
2.5
V
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
-6
-3
mV/°C
VGS = 10 V, ID = 13 A
VGS = 4.5 V, ID = 10 A
VGS = 10 V, ID = 13 A , TJ = 125 °C
VGS = 10 V, ID = 18 A
VGS = 4.5 V, ID = 17 A
VGS = 10 V, ID = 18 A , TJ = 125 °C
Q1
Q2
8.1 10
12 14.5
11 14.5
mΩ
2.8 5.0
3.5 5.2
4.0 7.1
VDS = 5 V, ID = 13 A
VDS = 5 V, ID = 18 A
Q1 53
Q2 113
S
Dynamic Characteristics
Ciss Input Capacitance
Coss
Output Capacitance
Crss Reverse Transfer Capacitance
Rg Gate Resistance
Q1:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q2:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
Q1
Q2
Q1
Q2
1205
1469
370
485
35
59
1605
2060
495
680
55
90
pF
pF
pF
Q1 0.3 1.6 3.2
Q2 0.2 1.4 3.0
Ω
Switching Characteristics
td(on)
Turn-On Delay Time
tr Rise Time
td(off)
Turn-Off Delay Time
tf Fall Time
Qg Total Gate Charge
Qg Total Gate Charge
Qgs Gate to Source Gate Charge
Qgd Gate to Drain “Miller” Charge
Q1:
VDD = 15 V, ID = 13 A, RGEN = 6 Ω
Q2:
VDD = 15 V, ID = 18 A, RGEN = 6 Ω
VGS = 0 V to 10 V Q1:
VDD = 15 V,
VGS = 0 V to 4.5 V ID = 13 A
Q2:
VDD = 15 V,
ID = 18 A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
9
7
18
14
ns
3
3
10
10
ns
20
24
36
40
ns
3
3
10
10
ns
17
24
24
34
nC
7.5
12
12
17
nC
3.9
3.3
nC
2.0
3.6
nC
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
2
www.fairchildsemi.com


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Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type Min Typ Max Units
Drain-Source Diode Characteristics
VGS = 0 V, IS = 13 A
(Note 2)
VSD
Source to Drain Diode
Forward Voltage
VGS = 0 V, IS = 2 A
VGS = 0 V, IS = 18 A
(Note 2)
(Note 2)
VGS = 0 V, IS = 2 A
(Note 2)
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
Q1:
IF = 13 A, di/dt = 100 A/μs
Q2:
IF = 18 A, di/dt = 300 A/μs
Q1
Q1
Q2
Q2
Q1
Q2
Q1
Q2
0.8 1.2
0.7 1.2
0.8 1.2
0.7 1.2
24 38
21 33
8 15
16 31
V
ns
nC
Notes:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
a. 57 °C/W when mounted on
a 1 in2 pad of 2 oz copper
b. 50 °C/W when mounted on
a 1 in2 pad of 2 oz copper
c. 125 °C/W when mounted on a
minimum pad of 2 oz copper
d. 120 °C/W when mounted on a
minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied with the negative Vgs rating.
4.
5.
EAS
EAS
of
of
61
48
mJ
mJ
is
is
based
based
on
on
starting
starting
TJ
TJ
=
=
25
25
oC;
oC;
N-ch:
N-ch:
L
L
=
=
3
3
mH,
mH,
IAS
IAS
=
=
6.4
5.7
A,
A,
VDD
VDD
=
=
30
30
V,
V,
VGS
VGS
=
=
10
10
V.
V.
100%
100%
test
test
at
at
L=
L=
0.1
0.1
mH,
mH,
IAS
IAS
=
=
20
17
A.
A.
6. Pulsed Id limited by junction temperature,td<=10uS. Please refer to SOA curve for more details.
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
3
www.fairchildsemi.com


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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
50
VGS = 10 V
VGS = 6 V
40
VGS = 4.5 V
30
VGS = 4 V
5
VGS = 3.5 V
4
3
20 2
VGS = 4 V
VGS = 6 V VGS = 4.5 V
10
0
0.0
VGS = 3.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0.5 1.0 1.5 2.0 2.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On Region Characteristics
1
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0 10 20
30
ID, DRAIN CURRENT (A)
VGS = 10 V
40 50
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
1.6
ID = 13 A
VGS = 10 V
1.4
30
ID = 13 A
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
25
1.2 20
TJ = 125 oC
1.0 15
0.8
0.6
-75 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. Normalized On Resistance
vs Junction Temperature
10
TJ = 25 oC
5
2468
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 4. On-Resistance vs Gate to
Source Voltage
10
50
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
40
VDS = 5 V
30
TJ = 150 oC
20
TJ = 25 oC
10
TJ = -55 oC
0
1234
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
5
50
VGS = 0 V
10
TJ = 150 oC
1
TJ = 25 oC
TJ = -55 oC
0.1
0.0
0.2 0.4 0.6 0.8 1.0
VSD, BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
4
www.fairchildsemi.com


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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
10
ID = 13 A
8
VDD = 10 V
6
VDD =15 V
VDD = 20 V
4
2000
1000
100
Ciss
Coss
2
0
0 3 6 9 12 15 18
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
f = 1 MHz
VGS = 0 V
Crss
10
0.1
1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure8. Capacitance vsDrain
to Source Voltage
25
20
TJ = 25 oC
15
TJ = 125 oC
10
TJ = 100 oC
5
1
0.01
0.1 1
tAV, TIME IN AVALANCHE (ms)
10
Figure9. UnclampedInductive
Switching Capability
40
100
100 μs
10
1 THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 125 oC/W
TA = 25 oC
0.01
0.01
0.1
1
1 ms
10 ms
100 ms
1s
10 s
DC
10 100200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
50
40
30
VGS = 4.5 V
20
VGS = 10 V
10
0
25
Limited by Package
RθJC = 5.0 oC/W
50 75 100 125
TC, CASE TEMPERATURE (oC)
150
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
1000
100
SINGLE PULSE
RθJA = 125 oC/W
10
1
0.110-4 10-3 10-2 10-1
1
10
t, PULSE WIDTH (sec)
100 1000
Figure 12. Single Pulse Maximum
Power Dissipation
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
5
www.fairchildsemi.com


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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
0.1
0.01
0.001
10-4
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
RθJA = 125 oC/W
(Note 1c)
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
10-3
10-2
10-1
1
10
t, RECTANGULAR PULSE DURATION (sec)
100
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
1000
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
6
www.fairchildsemi.com


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Typical Characteristics (Q2 N-Channel) TJ = 25 oC unlenss otherwise noted
60
VGS = 10 V
VGS = 4.5 V
45 VGS = 3.5 V
8
PULSE DURATION = 80 μs
VGS = 2.5 V
DUTY CYCLE = 0.5% MAX
6
30 VGS = 3 V
VGS = 2.5 V
15
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0.0 0.3 0.6 0.9 1.2 1.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 14. On-Region Characteristics
4
VGS = 3.5 V
2 VGS = 3 V
VGS = 4.5 V
VGS = 10 V
0
0 15 30 45 60
ID, DRAIN CURRENT (A)
Figure 15. Normalized on-Resistance vs Drain
Current and Gate Voltage
1.6
ID = 18 A
VGS = 10 V
1.4
1.2
1.0
0.8
0.6
-75 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 16. Normalized On-Resistance
vs Junction Temperature
20
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
15
ID = 18 A
10
TJ = 125 oC
5
TJ = 25 oC
0
2468
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 17. On-Resistance vs Gate to
Source Voltage
10
60
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
45
VDS = 5 V
30
TJ = 125 oC
TJ = 25 oC
15
TJ = -55 oC
0
1.0 1.5 2.0 2.5
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 18. Transfer Characteristics
3.0
100
VGS = 0 V
10
1
TJ = 125 oC
0.1
0.01
TJ = 25 oC
TJ = -55 oC
1E-3
0.0
0.2 0.4 0.6 0.8
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 19. Source to Drain Diode
Forward Voltage vs Source Current
1.0
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
7
www.fairchildsemi.com


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Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
10
ID = 17 A
8
VDD = 10 V
6
VDD = 15 V
4
VDD = 20 V
2
0
0 10 20
Qg, GATE CHARGE (nC)
30
Figure 20. Gate Charge Characteristics
10000
1000
Ciss
Coss
100
f = 1 MHz
VGS = 0 V
Crss
10
0.1
1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure 21. Capacitance vs Drain
to Source Voltage
100 80
TJ = 100 oC
10
TJ = 125 oC
TJ = 25 oC
60 VGS = 10 V
VGS = 4.5 V
40
Limited by Package
RθJC = 2.8 oC/W
20
1
1E-3
0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
100
Figure 22. Unclamped Inductive
Switching Capability
100
100 μs
10
1 THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 120 oC/W
TA = 25 oC
0.01
0.01
0.1
CURVE BENT ON
MEASURED DATA
1 10
1 ms
10 ms
100 ms
1s
10s
DC
100200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 24. Forward Bias Safe
Operating Area
0
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
Figure 23. Maximun Continuous Drain
Current vs Case Temperature
2000
1000
100
SINGLE PULSE
RθJA = 120 oC/W
10
1
0.150-4 10-3 10-2 10-1 100 101 100 1000
t, PULSE WIDTH (sec)
Figure 25. Single Pulse Maximum
Power Dissipation
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
8
www.fairchildsemi.com


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Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
2
1 DUTY CYCLE-DESCENDING ORDER
0.1
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
1E-3
SINGLE PULSE
RθJA = 120 oC/W
(Note 1d)
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
1E-4
10-4
10-3
10-2
10-1
100
101
100
t, RECTANGULAR PULSE DURATION (sec)
Figure 26. Junction-to-Ambient Transient Thermal Response Curve
1000
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
9
www.fairchildsemi.com


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Typical Characteristics (continued)
SyncFETTM Schottky body diode
Characteristics
Fairchild’s SyncFETTM process embeds a Schottky diode in
parallel with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
with a MOSFET. Figure 27 shows the reverse recovery
characteristic of the FDMS3669S.
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
20
15
didt = 300 A/μs
10
5
0
-5
-40 0 40 80 120 160
TIME (ns)
Figure 27. FDMS3669S SyncFETTM body
diode reverse recovery characteristic
10-2
10-3 TJ = 125 oC
10-4 TJ = 100 oC
10-5
10-6
0
TJ = 25 oC
5 10 15 20 25
VDS, REVERSE VOLTAGE (V)
30
Figure 28. SyncFETTM body diode reverse
leakage versus drain-source voltage
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
10
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Application Information
1. Switch Node Ringing Suppression
Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch
node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage
solution rings significantly less than competitor solutions under the same set of test conditions.
Power Stage Device
Competitors solution
Figure 29. Power Stage phase node rising edge, High Side Turn on
*Patent Pending
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
11
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Figure 30. Shows the Power Stage in a buck converter topology
2. Recommended PCB Layout Guidelines
As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power
train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2),
should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout proce-
dure is discussed below to maximize the electrical and thermal performance of the part.
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
Figure 31. Recommended PCB Layout
12
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Following is a guideline, not a requirement which the PCB designer should consider:
1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic
inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close
to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected
depending upon the application.
2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output
inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to
present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction
losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high
noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance
between the thermal and electrical performance of Power Stage.
3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace
resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be
directly in line (as shown in figure 31) with the inductor for space savings and compactness.
4. The PowerTrench® Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the
part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If
the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen
the high-frequency ringing.
5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side
gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the
MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate
current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses.
Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This
provides a very compact path for the drive signals and improves efficiency of the part.
6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise
transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET.
7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction.
Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as
ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected
from the backside via a network of low inductance vias.
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
13
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0.10 C
(2X)
8
5.10
4.90
PKG
CL
5
PKG CL
PIN # 1
INDICATOR
14
TOP VIEW
A
B
6.25
5.90
0.10 C
(2X)
0.63
2.15
4.16
2.13
0.63
4.00
CL
8 76
12 3
0.59
3.18
5.10
1.27 TYP
0.65 TYP
5
2.52
1.60
KEEP OUT AREA
0.00 CL
1.21
2.31
4 3.15
SEE
DETAIL A
RECOMMENDED LAND PATTERN
FOR SAWN / PUNCHED TYPE
SIDE VIEW
0.45
0.25
(6X)
0.65
0.38
1
3.16
2.80
23
0.10
0.05
0.70
0.36
CAB
C
4 1.34
1.12
4.08
3.70
0.66±.05
2.25
2.05
0.65 8
0.38
0.44
0.24
76
1.27
3.81
1.02
5 0.82
0.61
0.31
(8X)
BOTTOM VIEW
0.10 C
8X
0.08 C
1.10
0.90
0.35
0.15
0.05
0.00
C
SEATING
PLANE
(SCALE: 2X)


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0.10 C
(2X)
8
5.10
4.90
PKG
CL
5
PKG CL
6.25
5.90
SEE
DETAIL B
5.90
5.70
0.28
0.08
0.35
0.15
10°
14
0.41
0.21
(8X)
TOP VIEW
0.10 C
(2X)
(SCALE: 2X)
5.00
4.80
SIDE VIEW
SEE
DETAIL C
0.10 C
8X
0.08 C
1.10
0.90
(SCALE: 2X)
0.35
0.15
C
SEATING
PLANE
0.45
0.25
(6X)
0.65
0.38
1
3.16
2.80
23
0.70
0.36
0.10
0.05
4 1.34
1.12
4.08
3.70
0.66±.05
2.25
2.05
0.65
0.38
0.44
0.24
1.02
8 7 6 5 0.82
1.27
0.61
0.31
(8X)
3.81
BOTTOM VIEW
CAB
C
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC REGISTRATION, MO-240, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS OR
MOLD FLASH. MOLD FLASH OR BURRS DOES
NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: PQFN08EREV6.
G) FAIRCHILD SEMICONDUCTOR


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