FDMS3622S Datasheet PDF
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December 2011
FDMS3622S
PowerTrench® Power Stage
25V Asymmetric Dual N-Channel MOSFET
Features
Q1: N-Channel
„ Max rDS(on) = 5.0 mΩ at VGS = 10 V, ID = 17.5 A
„ Max rDS(on) = 5.7 mΩ at VGS = 4.5 V, ID = 16 A
Q2: N-Channel
„ Max rDS(on) = 1.4 mΩ at VGS = 10 V, ID = 34 A
„ Max rDS(on) = 1.6 mΩ at VGS = 4.5 V, ID = 32 A
„ Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
„ MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
„ RoHS Compliant
General Description
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Applications
„ Computing
„ Communications
„ General Purpose Point of Load
„ Notebook VCORE
Pin 1
Pin 1
G1 D1 D1 D1
D1
PHASE
(S1/D2)
G2S2
S2 S2
Top
Power 56
Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 4)
TC = 25 °C
TA = 25 °C
(Note 3)
TA = 25 °C
TA = 25 °C
Q1 Q2
25 25
±12 ±12
30
17.51a
70
341b
70 140
29
2.21a
1.01c
145
2.51b
1.01d
-55 to +150
Units
V
V
A
mJ
W
°C
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
571a
1251c
3.0
501b
1201d
1.9
°C/W
Device Marking
08OD
09OD
Device
FDMS3622S
Package
Power 56
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
©2011 Fairchild Semiconductor Corporation
FDMS3622S Rev.C2
1
www.fairchildsemi.com


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Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type Min Typ Max Units
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
IDSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
VDS = 20 V, VGS = 0 V
VGS = 12 V/-8 V, VDS= 0 V
Q1 25
Q2 25
Q1
Q2
Q1
Q2
Q1
Q2
V
12
24
mV/°C
1 μA
500 μA
±100
±100
nA
nA
On Characteristics
VGS(th)
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
rDS(on)
Drain to Source On Resistance
gFS Forward Transconductance
Dynamic Characteristics
Ciss Input Capacitance
Coss
Output Capacitance
Crss Reverse Transfer Capacitance
Rg Gate Resistance
VGS = VDS, ID = 250 μA
VGS = VDS, ID = 1 mA
Q1 0.8 1.2
Q2 1.1 1.4
2.0
2.2
V
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
-4
-4
mV/°C
VGS = 10 V, ID = 17.5 A
VGS = 4.5 V, ID = 16 A
VGS = 10 V, ID = 17.5 A,TJ =125 °C
VGS = 10 V, ID = 34 A
VGS = 4.5 V, ID = 32 A
VGS = 10 V, ID =34 A ,TJ =125 °C
Q1
Q2
3.8 5.0
4.4 5.7
5.4 7.0
mΩ
1.1 1.4
1.3 1.6
1.5 2.0
VDS = 5 V, ID = 17.5 A
VDS = 5 V, ID = 34 A
Q1 100
Q2 272
S
Q1:
VDS = 13 V, VGS = 0 V, f = 1 MHZ
Q2:
VDS = 13 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
1570
5565
448
1405
61
182
0.4
0.8
pF
pF
pF
Ω
Switching Characteristics
td(on)
Turn-On Delay Time
tr Rise Time
td(off)
Turn-Off Delay Time
tf Fall Time
Qg Total Gate Charge
Qg Total Gate Charge
Qgs Gate to Source Gate Charge
Qgd Gate to Drain “Miller” Charge
Q1:
VDD = 13 V, ID = 17.5 A, RGEN = 6 Ω
Q2:
VDD = 13 V, ID = 34 A, RGEN = 6 Ω
VGS = 0 V to 10 V Q1
VDD = 13 V,
VGS = 0 V to 4.5 V ID = 17.5 A
Q2
VDD = 13 V,
ID = 34 A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
7
14
2
7
23
48
2
6
26
86
12
40
3.3
12
2.7
10
ns
ns
ns
ns
nC
nC
nC
nC
©2011 Fairchild Semiconductor Corporation
FDMS3622S Rev.C2
2
www.fairchildsemi.com


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Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type Min Typ Max Units
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage
VGS = 0 V, IS = 17.5 A
VGS = 0 V, IS = 34 A
(Note 2) Q1
(Note 2) Q2
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
Q1
IF = 17.5 A, di/dt = 100 A/μs
Q2
IF = 34 A, di/dt = 300 A/μs
Q1
Q2
Q1
Q2
0.8 1.2
0.8 1.2
23
35
9
43
V
ns
nC
Notes:
1.RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
a. 57 °C/W when mounted on
a 1 in2 pad of 2 oz copper
b. 50 °C/W when mounted on
a 1 in2 pad of 2 oz copper
c. 125 °C/W when mounted on a
minimum pad of 2 oz copper
d. 120 °C/W when mounted on a
minimum pad of 2 oz copper
2 Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Q1 :EAS of 29 mJ is based on starting TJ = 25 oC; N-ch: L = 1.2 mH, IAS = 7 A, VDD = 23 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 16 A.
Q2: EAS of 145 mJ is based on starting TJ = 25 oC; N-ch: L = 0.9 mH, IAS = 18 A, VDD = 23 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 39 A.
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
©2011 Fairchild Semiconductor Corporation
FDMS3622S Rev.C2
3
www.fairchildsemi.com


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Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
70
60
50
40
30
20
10
0
0.0
VGS = 10 V
VGS = 4.5 V
VGS = 3.5 V
VGS = 3 V
VGS = 2.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0.3 0.6 0.9 1.2
VDS, DRAIN TO SOURCE VOLTAGE (V)
1.5
Figure 1. On Region Characteristics
3.0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
2.5
VGS = 2.5 V
2.0
1.5
VGS = 3 V
1.0
0.5
0
VGS = 3.5 V VGS = 4.5 V VGS = 10 V
10 20 30 40 50 60 70
ID, DRAIN CURRENT (A)
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
1.8
ID = 17.5 A
1.6 VGS = 10 V
1.4
1.2
1.0
0.8
0.6
-75 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. Normalized On Resistance
vs Junction Temperature
20
ID = 17.5 A
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
16
12
8
TJ = 125 oC
4
TJ = 25 oC
0
2 3 4 5 6 7 8 9 10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 4. On-Resistance vs Gate to
Source Voltage
70
PULSE DURATION = 80 μs
60 DUTY CYCLE = 0.5% MAX
VDS = 5 V
50
40
TJ = 150 oC
30
TJ = 25 oC
20
TJ = -55 oC
10
0
0.5 1.0 1.5 2.0 2.5 3.0
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
70
VGS = 0 V
10
TJ = 150 oC
1
0.1
0.01
TJ = 25 oC
TJ = -55 oC
0.001
0.0
0.2 0.4 0.6 0.8 1.0
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
1.2
©2011 Fairchild Semiconductor Corporation
FDMS3622S Rev.C2
4
www.fairchildsemi.com


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Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
10
ID = 17.5 A
8
6
4
VDD = 10 V
VDD = 15 V
VDD = 13 V
2
0
0 4 8 12 16 20 24 28
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
50
TJ = 25 oC
10
TJ = 100 oC
TJ = 125 oC
1
0.001
0.01 0.1
1
tAV, TIME IN AVALANCHE (ms)
10
50
Figure9. UnclampedInductive
Switching Capability
2000
1000
100
Ciss
Coss
f = 1 MHz
Crss
VGS = 0 V
10
0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure8. CapacitancevsDrain
to Source Voltage
80
70
60
VGS = 10 V
50
VGS = 4.5 V
40
30
20
Limited by Package
10 RθJC = 3.0 oC/W
0
25 50 75 100 125
TC, CASE TEMPERATURE (oC)
150
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
100
100 μs
10
1 THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 125 oC/W
TA = 25 oC
0.01
0.01
0.1
1
1 ms
10 ms
100 ms
1s
10s
DC
10 100200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
1000
100
SINGLE PULSE
RθJA = 125 oC/W
10
1
0.5
10-4 10-3 10-2 10-1
1
10
t, PULSE WIDTH (sec)
100 1000
Figure 12. Single Pulse Maximum
Power Dissipation
©2011 Fairchild Semiconductor Corporation
FDMS3622S Rev.C2
5
www.fairchildsemi.com


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Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
0.1 0.02
0.01
PDM
0.01
0.001
10-4
SINGLE PULSE
RθJA = 125 oC/W
(Note 1b)
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
10-3
10-2
10-1
1
10
t, RECTANGULAR PULSE DURATION (sec)
100
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
1000
©2011 Fairchild Semiconductor Corporation
FDMS3622S Rev.C2
6
www.fairchildsemi.com


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Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted
140
VGS = 10 V
120 VGS = 4.5 V
100 VGS = 3.5 V
VGS = 3 V
80
60
VGS = 2.5 V
40
20
0
0.0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0.3 0.6 0.9 1.2 1.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 14. On-Region Characteristics
1.6
ID = 34 A
VGS = 10 V
1.4
1.2
1.0
0.8
0.6
-75 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 16. Normalized On-Resistance
vs Junction Temperature
4
PULSE DURATION = 80 μs
VGS = 2.5 V DUTY CYCLE = 0.5% MAX
3
2 VGS = 3 V
VGS = 3.5 V
1
VGS = 4.5 V VGS = 10 V
0
0 20 40 60 80 100 120 140
ID, DRAIN CURRENT (A)
Figure 15. Normalized on-Resistance vs Drain
Current and Gate Voltage
5
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
4
ID = 34 A
3
2
TJ = 125 oC
1
TJ = 25 oC
0
2 4 6 8 10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 17. On-Resistance vs Gate to
Source Voltage
140
PULSE DURATION = 80 μs
120 DUTY CYCLE = 0.5% MAX
VDS = 5 V
100
80
60
TJ = 125 oC
TJ = 25 oC
40
TJ = -55 oC
20
0
1.0 1.5 2.0 2.5 3.0
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 18. Transfer Characteristics
200
100 VGS = 0 V
10
1
0.1
0.01
TJ = 125 oC
TJ = 25 oC
TJ = -55 oC
0.001
0.0 0.2 0.4 0.6 0.8
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 19. Source to Drain Diode
Forward Voltage vs Source Current
1.0
©2011 Fairchild Semiconductor Corporation
FDMS3622S Rev.C2
7
www.fairchildsemi.com


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Typical Characteristics (Q2 N-Channel) TJ = 25°C unless otherwise noted
10
ID = 34 A
8
6
4
2
VDD = 10 V
VDD = 13 V
VDD = 15 V
0
0 15 30 45 60 75 90
Qg, GATE CHARGE (nC)
10000
1000
Ciss
Coss
f = 1 MHz
VGS = 0 V
Crss
100
0.1
1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure 20. Gate Charge Characteristics
Figure 21. Capacitance vs Drain
to Source Voltage
100
TJ = 25 oC
10 TJ = 100 oC
TJ = 125 oC
1
0.001
0.01 0.1 1 10 100
tAV, TIME IN AVALANCHE (ms)
1000
Figure 22. Unclamped Inductive
Switching Capability
180
150
VGS = 10 V
120
VGS = 4.5 V
90
60
Limited by Package
30
RθJC = 1.9 oC/W
0
25 50 75 100 125
TC, CASE TEMPERATURE (oC)
150
Figure 23. Maximum Continuous Drain
Current vs Case Temperature
200
100 100 μs
10
1
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 120 oC/W
TA = 25 oC
0.01
0.01
0.1
1
10
VDS, DRAIN to SOURCE VOLTAGE (V)
1 ms
10 ms
100 ms
1s
10s
DC
100
Figure 24. Forward Bias Safe
Operating Area
3000
1000
100
SINGLE PULSE
RθJA = 120 oC/W
10
1
0.5
10-4
10-3
10-2 10-1
1
10
t, PULSE WIDTH (sec)
100 1000
Figure 25. Single Pulse Maximum Power
Dissipation
©2011 Fairchild Semiconductor Corporation
FDMS3622S Rev.C2
8
www.fairchildsemi.com


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Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted
2
1 DUTY CYCLE-DESCENDING ORDER
0.1
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.001
0.0001
10-4
PDM
SINGLE PULSE
RθJA = 120 oC/W
(Note 1b)
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
10-3
10-2
10-1
1
10
t, RECTANGULAR PULSE DURATION (sec)
100
Figure 26. Junction-to-Ambient Transient Thermal Response Curve
1000
©2011 Fairchild Semiconductor Corporation
FDMS3622S Rev.C2
9
www.fairchildsemi.com


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Typical Characteristics (continued)
SyncFET Schottky body diode
Characteristics
Fairchild’s SyncFET process embeds a Schottky diode in parallel
with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
with a MOSFET. Figure 27 shows the reverse recovery
characteristic of the FDMS3622S.
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
40
35
30
25
20 di/dt = 300 A/μs
15
10
5
0
-5
0 40 80 120 160 200 240 280 320 360
TIME (ns)
10-2
10-3
10-4
10-5
10-6
0
TJ = 125 oC
TJ = 100 oC
TJ = 25 oC
5 10 15 20
VDS, REVERSE VOLTAGE (V)
25
Figure 27. FDMS3622S SyncFET body
diode reverse recovery characteristic
Figure 28. SyncFET body diode reverse
leakage versus drain-source voltage
©2011 Fairchild Semiconductor Corporation
FDMS3622S Rev.C2
10
www.fairchildsemi.com


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0.10 C
(2X)
8
5.10
4.90
PKG
CL
5
PKG CL
PIN # 1
INDICATOR
14
TOP VIEW
A
B
6.25
5.90
0.10 C
(2X)
0.63
2.15
4.16
2.13
0.63
4.00
CL
8 76
12 3
0.59
3.18
5.10
1.27 TYP
0.65 TYP
5
2.52
1.60
KEEP OUT AREA
0.00 CL
1.21
2.31
4 3.15
SEE
DETAIL A
RECOMMENDED LAND PATTERN
FOR SAWN / PUNCHED TYPE
SIDE VIEW
0.45
0.25
(6X)
0.65
0.38
1
3.16
2.80
23
0.10
0.05
0.70
0.36
CAB
C
4 1.34
1.12
4.08
3.70
0.66±.05
2.25
2.05
0.65 8
0.38
0.44
0.24
76
1.27
3.81
1.02
5 0.82
0.61
0.31
(8X)
BOTTOM VIEW
0.10 C
8X
0.08 C
1.10
0.90
0.35
0.15
0.05
0.00
C
SEATING
PLANE
(SCALE: 2X)


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0.10 C
(2X)
8
5.10
4.90
PKG
CL
5
PKG CL
6.25
5.90
SEE
DETAIL B
5.90
5.70
0.28
0.08
0.35
0.15
10°
14
0.41
0.21
(8X)
TOP VIEW
0.10 C
(2X)
(SCALE: 2X)
5.00
4.80
SIDE VIEW
SEE
DETAIL C
0.10 C
8X
0.08 C
1.10
0.90
(SCALE: 2X)
0.35
0.15
C
SEATING
PLANE
0.45
0.25
(6X)
0.65
0.38
1
3.16
2.80
23
0.70
0.36
0.10
0.05
4 1.34
1.12
4.08
3.70
0.66±.05
2.25
2.05
0.65
0.38
0.44
0.24
1.02
8 7 6 5 0.82
1.27
0.61
0.31
(8X)
3.81
BOTTOM VIEW
CAB
C
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC REGISTRATION, MO-240, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS OR
MOLD FLASH. MOLD FLASH OR BURRS DOES
NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: PQFN08EREV6.
G) FAIRCHILD SEMICONDUCTOR


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