Atmel Electronic Components Datasheet



ATmega1284

8-bit AVR Microcontrollers


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8-bit AVR Microcontrollers
ATmega1284
DATASHEET COMPLETE
Introduction
The Atmel® ATmega1284 is a low-power CMOS 8-bit microcontroller based
on the AVR® enhanced RISC architecture. By executing powerful
instructions in a single clock cycle, the ATmega1284 achieves throughputs
close to 1MIPS per MHz. This empowers system designer to optimize the
device for power consumption versus processing speed.
Feature
High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Family
Advanced RISC Architecture
131 Powerful Instructions
Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 20 MIPS Throughput at 20MHz
On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory Segments
128KBytes of In-System Self-Programmable Flash Program
Memory
4KBytes EEPROM
16KBytes Internal SRAM
Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
Data Retention: 20 Years at 85°C/100 Years at 25°C(1)
Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
Programming Lock for Software Security
Atmel QTouch® Library Support
Capacitive Touch Buttons, Sliders and Wheels
QTouch and QMatrix acquisition
Up to 64 Sense Channels
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JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the JTAG Standard
Extensive On-chip Debug Support
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
Two 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode
Real Time Counter with Separate Oscillator
Eight PWM Channels
8-channel 10-bit ADC
• Differential Mode with Selectable Gain at 1×, 10× or 200×
One Byte-oriented 2-wire Serial Interface (Philips I2C compatible)
Two Programmable Serial USART
One Master/Slave SPI Serial Interface
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Interrupt and Wake-up on Pin Change
Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and
Extended Standby
I/O and Packages
32 Programmable I/O Lines
40-pin PDIP
44-lead TQFP
44-pad VQFN/QFN
Operating Voltage:
1.8 - 5.5V
Speed Grades
0 - 4MHz @ 1.8V - 5.5V
0 - 10MHz @ 2.7V - 5.5V
0 - 20MHz @ 4.5 - 5.5V
Power Consumption at 1MHz, 1.8V, 25°C
Active Mode: 0.4mA
Power-down Mode: 0.1μA
Power-save Mode: 0.6μA (Including 32kHz RTC)
Note: 
1. Refer to Data Retention
Related Links
Data Retention on page 18
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Table of Contents
Introduction......................................................................................................................1
Feature............................................................................................................................ 1
1. Description.................................................................................................................9
2. Configuration Summary........................................................................................... 10
3. Ordering Information ............................................................................................... 11
4. Block Diagram......................................................................................................... 12
5. Pin Configurations................................................................................................... 13
5.1. Pinout......................................................................................................................................... 13
5.2. Pin Descriptions..........................................................................................................................14
6. I/O Multiplexing........................................................................................................ 16
7. General Information................................................................................................. 18
7.1. Resources.................................................................................................................................. 18
7.2. Data Retention............................................................................................................................18
7.3. About Code Examples................................................................................................................18
7.4. Capacitive Touch Sensing.......................................................................................................... 18
8. AVR CPU Core........................................................................................................ 19
8.1. Overview.....................................................................................................................................19
8.2. ALU – Arithmetic Logic Unit........................................................................................................20
8.3. Status Register...........................................................................................................................20
8.4. General Purpose Register File................................................................................................... 22
8.5. Stack Pointer.............................................................................................................................. 23
8.6. Accessing 16-bit Registers.........................................................................................................25
8.7. Instruction Execution Timing...................................................................................................... 26
8.8. Reset and Interrupt Handling..................................................................................................... 26
9. AVR Memories.........................................................................................................29
9.1. Overview.....................................................................................................................................29
9.2. In-System Reprogrammable Flash Program Memory................................................................ 29
9.3. SRAM Data Memory...................................................................................................................30
9.4. EEPROM Data Memory............................................................................................................. 31
9.5. I/O Memory.................................................................................................................................32
9.6. Register Description................................................................................................................... 32
10. System Clock and Clock Options............................................................................ 41
10.1. Clock Systems and Their Distribution.........................................................................................41
10.2. Clock Sources............................................................................................................................ 42
10.3. Low Power Crystal Oscillator......................................................................................................44


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10.4. Full Swing Crystal Oscillator.......................................................................................................45
10.5. Low Frequency Crystal Oscillator...............................................................................................46
10.6. Calibrated Internal RC Oscillator................................................................................................47
10.7. 128kHz Internal Oscillator.......................................................................................................... 48
10.8. External Clock............................................................................................................................ 49
10.9. Timer/Counter Oscillator.............................................................................................................50
10.10. Clock Output Buffer....................................................................................................................50
10.11. System Clock Prescaler............................................................................................................. 50
10.12. Register Description...................................................................................................................51
11. PM - Power Management and Sleep Modes........................................................... 55
11.1. Overview.....................................................................................................................................55
11.2. Sleep Modes...............................................................................................................................55
11.3. BOD Disable...............................................................................................................................56
11.4. Idle Mode....................................................................................................................................56
11.5. ADC Noise Reduction Mode.......................................................................................................56
11.6. Power-Down Mode.....................................................................................................................57
11.7. Power-save Mode.......................................................................................................................57
11.8. Standby Mode............................................................................................................................ 58
11.9. Extended Standby Mode............................................................................................................ 58
11.10. Power Reduction Registers........................................................................................................58
11.11. Minimizing Power Consumption................................................................................................. 58
11.12. Register Description................................................................................................................... 60
12. SCRST - System Control and Reset....................................................................... 67
12.1. Resetting the AVR...................................................................................................................... 67
12.2. Reset Sources............................................................................................................................67
12.3. Power-on Reset..........................................................................................................................68
12.4. External Reset............................................................................................................................69
12.5. Brown-out Detection...................................................................................................................69
12.6. Watchdog System Reset............................................................................................................ 70
12.7. Internal Voltage Reference.........................................................................................................70
12.8. Watchdog Timer......................................................................................................................... 71
12.9. Register Description................................................................................................................... 73
13. Interrupts................................................................................................................. 77
13.1. Overview.....................................................................................................................................77
13.2. Interrupt Vectors in ATmega1284............................................................................................... 77
13.3. Register Description................................................................................................................... 80
14. External Interrupts................................................................................................... 83
14.1. EXINT - External Interrupts........................................................................................................ 83
15. I/O-Ports.................................................................................................................. 95
15.1. Overview.....................................................................................................................................95
15.2. Ports as General Digital I/O........................................................................................................96
15.3. Alternate Port Functions.............................................................................................................99
15.4. Register Description................................................................................................................. 112
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16. TC0 - 8-bit Timer/Counter0 with PWM...................................................................127
16.1. Features................................................................................................................................... 127
16.2. Overview...................................................................................................................................127
16.3. Timer/Counter Clock Sources.................................................................................................. 129
16.4. Counter Unit............................................................................................................................. 129
16.5. Output Compare Unit................................................................................................................130
16.6. Compare Match Output Unit.....................................................................................................132
16.7. Modes of Operation..................................................................................................................133
16.8. Timer/Counter Timing Diagrams...............................................................................................137
16.9. Register Description................................................................................................................. 139
17. TC1/3 - 16-bit Timer/Counter1/3 with PWM...........................................................152
17.1. Overview...................................................................................................................................152
17.2. Features................................................................................................................................... 152
17.3. Block Diagram.......................................................................................................................... 152
17.4. Definitions.................................................................................................................................153
17.5. Registers.................................................................................................................................. 154
17.6. Accessing 16-bit Registers.......................................................................................................154
17.7. Timer/Counter Clock Sources.................................................................................................. 157
17.8. Counter Unit............................................................................................................................. 157
17.9. Input Capture Unit.................................................................................................................... 158
17.10. Output Compare Units............................................................................................................. 161
17.11. Compare Match Output Unit.....................................................................................................163
17.12. Modes of Operation..................................................................................................................164
17.13. Timer/Counter Timing Diagrams.............................................................................................. 172
17.14. Register Description.................................................................................................................173
18. Timer/Counter 0, 1, 3 Prescalers...........................................................................206
18.1. Internal Clock Source............................................................................................................... 206
18.2. Prescaler Reset........................................................................................................................206
18.3. External Clock Source..............................................................................................................206
18.4. Register Description................................................................................................................. 207
19. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation................... 209
19.1. Features................................................................................................................................... 209
19.2. Overview...................................................................................................................................209
19.3. Timer/Counter Clock Sources...................................................................................................211
19.4. Counter Unit..............................................................................................................................211
19.5. Output Compare Unit................................................................................................................212
19.6. Compare Match Output Unit.....................................................................................................214
19.7. Modes of Operation..................................................................................................................215
19.8. Timer/Counter Timing Diagrams...............................................................................................219
19.9. Asynchronous Operation of Timer/Counter2............................................................................ 220
19.10. Timer/Counter Prescaler.......................................................................................................... 222
19.11. Register Description................................................................................................................. 222
20. SPI – Serial Peripheral Interface........................................................................... 235
20.1. Features................................................................................................................................... 235
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20.2. Overview...................................................................................................................................235
20.3. SS Pin Functionality................................................................................................................. 239
20.4. Data Modes.............................................................................................................................. 239
20.5. Register Description................................................................................................................. 240
21. USART - Universal Synchronous Asynchronous Receiver Transceiver................245
21.1. Features................................................................................................................................... 245
21.2. Overview...................................................................................................................................245
21.3. Block Diagram.......................................................................................................................... 245
21.4. Clock Generation......................................................................................................................246
21.5. Frame Formats.........................................................................................................................249
21.6. USART Initialization..................................................................................................................250
21.7. Data Transmission – The USART Transmitter......................................................................... 251
21.8. Data Reception – The USART Receiver.................................................................................. 253
21.9. Asynchronous Data Reception.................................................................................................257
21.10. Multi-Processor Communication Mode.................................................................................... 259
21.11. Examples of Baud Rate Setting............................................................................................... 260
21.12. Register Description.................................................................................................................263
22. USARTSPI - USART in SPI Mode.........................................................................274
22.1. Features................................................................................................................................... 274
22.2. Overview...................................................................................................................................274
22.3. Clock Generation......................................................................................................................274
22.4. SPI Data Modes and Timing.....................................................................................................275
22.5. Frame Formats.........................................................................................................................275
22.6. Data Transfer............................................................................................................................277
22.7. AVR USART MSPIM vs. AVR SPI............................................................................................278
22.8. Register Description................................................................................................................. 279
23. TWI - 2-wire Serial Interface..................................................................................280
23.1. Features................................................................................................................................... 280
23.2. Two-Wire Serial Interface Bus Definition..................................................................................280
23.3. Data Transfer and Frame Format.............................................................................................281
23.4. Multi-master Bus Systems, Arbitration and Synchronization....................................................284
23.5. Overview of the TWI Module.................................................................................................... 286
23.6. Using the TWI...........................................................................................................................288
23.7. Transmission Modes................................................................................................................ 291
23.8. Multi-master Systems and Arbitration.......................................................................................309
23.9. Register Description................................................................................................................. 311
24. AC - Analog Comparator....................................................................................... 319
24.1. Overview...................................................................................................................................319
24.2. Analog Comparator Multiplexed Input...................................................................................... 319
24.3. Register Description................................................................................................................. 320
25. ADC - Analog to Digital Converter.........................................................................325
25.1. Features................................................................................................................................... 325
25.2. Overview...................................................................................................................................325
25.3. Starting a Conversion...............................................................................................................327
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25.4. Prescaling and Conversion Timing...........................................................................................328
25.5. Changing Channel or Reference Selection.............................................................................. 331
25.6. ADC Noise Canceler................................................................................................................ 333
25.7. ADC Conversion Result............................................................................................................337
25.8. Register Description................................................................................................................. 339
26. JTAG Interface and On-chip Debug System..........................................................351
26.1. Features................................................................................................................................... 351
26.2. Overview...................................................................................................................................351
26.3. TAP – Test Access Port............................................................................................................ 352
26.4. TAP Controller.......................................................................................................................... 353
26.5. Using the Boundary-scan Chain...............................................................................................354
26.6. Using the On-chip Debug System............................................................................................ 354
26.7. On-chip Debug Specific JTAG Instructions.............................................................................. 355
26.8. Using the JTAG Programming Capabilities.............................................................................. 355
26.9. Bibliography..............................................................................................................................356
26.10. IEEE 1149.1 (JTAG) Boundary-scan........................................................................................356
26.11. Data Registers..........................................................................................................................357
26.12. Boundry-scan Specific JTAG Instructions................................................................................ 358
26.13. Boundary-scan Chain...............................................................................................................360
26.14. ATmega1284 Boundary-scan Order.........................................................................................363
26.15. Boundary-scan Description Language Files............................................................................ 365
26.16. Register Description.................................................................................................................365
27. BTLDR - Boot Loader Support – Read-While-Write Self-Programming................ 370
27.1. Features................................................................................................................................... 370
27.2. Overview...................................................................................................................................370
27.3. Application and Boot Loader Flash Sections............................................................................370
27.4. Read-While-Write and No Read-While-Write Flash Sections...................................................371
27.5. Entering the Boot Loader Program...........................................................................................373
27.6. Boot Loader Lock Bits.............................................................................................................. 374
27.7. Addressing the Flash During Self-Programming...................................................................... 375
27.8. Self-Programming the Flash.....................................................................................................376
27.9. Register Description................................................................................................................. 384
28. MEMPROG- Memory Programming......................................................................387
28.1. Program And Data Memory Lock Bits...................................................................................... 387
28.2. Fuse Bits...................................................................................................................................388
28.3. Signature Bytes........................................................................................................................ 391
28.4. Calibration Byte........................................................................................................................ 391
28.5. Serial Number...........................................................................................................................391
28.6. Page Size................................................................................................................................. 391
28.7. Parallel Programming Parameters, Pin Mapping, and Commands.......................................... 392
28.8. Parallel Programming...............................................................................................................394
28.9. Serial Downloading...................................................................................................................401
28.10. Programming Via the JTAG Interface.......................................................................................406
29. Electrical Characteristics....................................................................................... 420
29.1. Absolute Maximum Ratings......................................................................................................420
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29.2. DC Characteristics....................................................................................................................420
29.3. Speed Grades.......................................................................................................................... 422
29.4. Clock Characteristics................................................................................................................423
29.5. System and Reset Characteristics........................................................................................... 424
29.6. External interrupts characteristics............................................................................................ 425
29.7. SPI Timing Characteristics....................................................................................................... 426
29.8. Two-wire Serial Interface Characteristics................................................................................. 427
29.9. ADC characteristics..................................................................................................................429
29.10. Parallel Programming Characteristics......................................................................................433
30. Typical Characteristics...........................................................................................435
30.1. Active Supply Current...............................................................................................................435
30.2. Idle Supply Current...................................................................................................................437
30.3. Supply Current of I/O Modules................................................................................................. 439
30.4. Power-down Supply Current.....................................................................................................440
30.5. Power-save Supply Current......................................................................................................441
30.6. Standby Supply Current........................................................................................................... 442
30.7. Pin Pull-Up................................................................................................................................442
30.8. Pin Driver Strength................................................................................................................... 445
30.9. Pin Threshold and Hysteresis...................................................................................................447
30.10. BOD Threshold........................................................................................................................ 449
30.11. Internal Oscillator Speed.......................................................................................................... 451
30.12. Current Consumption of Peripheral Units................................................................................ 453
30.13. Current Consumption in Reset and Reset Pulse Width........................................................... 456
31. Register Summary.................................................................................................458
32. Instruction Set Summary....................................................................................... 462
33. Packaging Information...........................................................................................466
33.1. 40-pin PDIP.............................................................................................................................. 466
33.2. 44-pin TQFP.............................................................................................................................467
33.3. 44-pin VQFN.............................................................................................................................468
34. Datasheet Revision History................................................................................... 469
34.1. Rev. B – 08/2016...................................................................................................................... 469
34.2. Rev. A – 05/2016...................................................................................................................... 469
35. Errata.....................................................................................................................470
35.1. Rev. B....................................................................................................................................... 470
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1. Description
The Atmel® ATmega1284 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega1284 achieves
throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power
consumption versus processing speed.
The Atmel AVR® core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers
to be accessed in a single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega1284 provides the following features: 128Kbytes of In-System Programmable Flash with
Read-While-Write capabilities, 4Kbytes EEPROM, 16Kbytes SRAM, 32 general purpose I/O lines, 32
general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare
modes and PWM, two serial programmable USARTs , one byte-oriented 2-wire Serial Interface (I2C), a 8-
channel 10-bit ADC with optional differential input stage with programmable gain, a programmable
Watchdog Timer with internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test
interface, also used for accessing the On-chip Debug system and programming and six software
selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters,
SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents
but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In
Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base
while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O
modules except asynchronous timer and ADC to minimize switching noise during ADC conversions. In
Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. This
allows very fast start-up combined with low power consumption. In Extended Standby mode, both the
main oscillator and the asynchronous timer continue to run.
Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality
into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and
includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS)
technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you
to explore, develop and debug your own touch applications.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP
Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
The Boot program can use any interface to download the application program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega1284 is a powerful microcontroller that
provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega1284 is supported with a full suite of program and system development tools including: C
Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
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2. Configuration Summary
The table below compares the device series of feature and pin compatible devices, providing a seamless
migration path.
Table 2-1. Configuration Summary and Device Comparison
Features
ATmega164A
ATmega324A
ATmega644A
ATmega1284
Pin Count
40/44/49
40/44/49
40/44
40/44
Flash (Bytes)
16K
32K
64K 128K
SRAM (Bytes)
1K
2K
4K 16K
EEPROM (Bytes)
512
1K
2K
4K
General Purpose
32
32
32
32
I/O Lines
SPI
TWI (I2C)
1111
1111
USART
2222
ADC
10-bit 15ksps
10-bit 15ksps
10-bit 15ksps
10-bit 15ksps
ADC Channels
8
8
8
8
Analog Comparator
1
1
1
1
8-bit Timer/
2
2
2
2
Counters
16-bit Timer/
1
1
1
2
Counters
PWM channels
6
6
6
8
Packages
PDIP
PDIP
PDIP
PDIP
TQFP
TQFP
TQFP
TQFP
VQFN/QFN
VQFN/QFN
VQFN/QFN
VQFNQFN
DRQFN
DRQFN
VFBGA
VFBGA
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3. Ordering Information
Speed [MHz](3) Power Supply [V]
20 1.8 - 5.5
Ordering Code(2)
ATmega1284A-AU
ATmega1284A-AUR(4)
ATmega1284A-PU
ATmega1284A-MU
ATmega1284A-MUR(4)
Package(1)
44A
44A
40P6
44M1
44M1
Operational Range
Industrial
(-40°C to 85°C)
Note: 
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Refer to Speed Grades for Speed vs. VCC
4. Tape & Reel.
Package Type
40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44A 44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
44M1 44-pad, 7 × 7 × 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat No-
Lead (VQFN)
Related Links
Speed Grades on page 422
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4. Block Diagram
Figure 4-1. Block Diagram
TCK
TMS
TDI
JTAG
TDO
CPU
OCD
SRAM
TOSC1
TOSC2
XTAL 1
XTAL 2
Clock generation
32.768kHz
XOSC
16MHz LP
XOSC
8MHz
Calib RC
128kHz int
osc
External
clock
VCC
RESET
GND
Power
Supervision
POR/BOD &
RESET
ADC[7:0]
AREF
NVM
programming
Power
management
and clock
control
Watchdog
Timer
ADC
PCINT[31:0]
INT[2:0]
OC1A/B
T1
ICP1
OC3A/B
T3
ICP3
OC2A
OC2B
EXTINT
TC 1
(16-bit)
TC 3
(16-bit)
TC 2
(8-bit async)
D
A
T
A
B
U
S
FLASH
EEPROM
EEPROMIF
Internal
Reference
USART 0
USART 1
TWI
I I/O
N PORTS
/
O
U
T GPIOR[2:0]
D
A
TC 0
T (8-bit)
A
B
U SPI
S
AC
RxD0
TxD0
XCK0
RxD1
TxD1
XCK1
SDA
SCL
PA [7:0]
PB[7:0]
PC[7:0]
PD[7:0]
T0
OC0A
OC0B
MISO
MOSI
SCK
SS
AIN0
AIN1
ACO
ADCMUX
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5. Pin Configurations
5.1. Pinout
5.1.1. PDIP
(PCINT8/XCK0/T0)
(PCINT9/CLKO/T1)
(PCINT10/INT2/AIN0)
(PCINT11/OC0A/AIN1)
(PCINT12/OC0B/
(PCINT13/MOSI)
(PCINT14/OC3A/MISO)
(PCINT15/OC3B/SCK)
XTAL2
XTAL1
(PCINT24/RXD0/T3)
(PCINT25/TXD0)
(PCINT26/RXD1/INT0)
(PCINT27/TXD1/INT1)
(PCINT28/XCK1/OC1B)
(PCINT29/OC1A)
(PCINT30/OC2B/ICP1)
Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
(ADC0/PCINT0)
(ADC1/PCINT1)
(ADC2/PCINT2)
(ADC3/PCINT3)
(ADC4/PCINT4)
(ADC5/PCINT5)
(ADC6/PCINT6)
(ADC7/PCINT7)
(TOSC2/PCINT23)
(TOSC1/PCINT22)
(TDI/PCINT21)
(TDO/PCINT20)
(TMS/PCINT19)
(TCK/PCINT18)
(SDA/PCINT17)
(SCL/PCINT16)
(OC2A/PCINT31)
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5.1.2. TQFN and QFN
Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
(PCINT13/MOSI) PB5
(PCINT14/OC3A/MISO) PB6
(PCINT15/OC3B/SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(PCINT24/RXD0/T3) PD0
(PCINT25/TXD0) PD1
(PCINT26/RXD1/INT0) PD2
1
2
3
4
5
6
7
8
9
10
11
33 PA4 (ADC4/PCINT4)
32 PA5 (ADC5/PCINT5)
31 PA6 (ADC6/PCINT6)
30 PA7 (ADC7/PCINT7)
29 AREF
28 GND
27 AVCC
26 PC7 (TOSC2/PCINT23)
25 PC6 (TOSC1/PCINT22)
24 PC5 (TDI/PCINT21)
23 PC4 (TDO/PCINT20)
5.2. Pin Descriptions
5.2.1. VCC
Digital supply voltage.
5.2.2. GND
Ground.
5.2.3. Port A (PA[7:0])
This port serves as analog inputs to the Analog-to-digital Converter.
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This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
5.2.4.
Port B (PB[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port also serves the functions of various special features.
5.2.5.
Port C (PC[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port also serves the functions of the JTAG interface, along with special features.
5.2.6.
Port D (PD[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port also serves the functions of various special features.
5.2.7.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if
the clock is not running. Shorter pulses are not guaranteed to generate a reset.
5.2.8. XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
5.2.9. XTAL2
Output from the inverting Oscillator amplifier.
5.2.10.
AVCC
AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through
a low-pass filter.
5.2.11. AREF
This is the analog reference pin for the Analog-to-digital Converter.
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6. I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions.
The following table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 6-1. PORT Function Multiplexing
32-pin
40-pin
TQFP/ QFN/ PIPD Pin
MLF Pin # #
16
27
38
49
5 10
6 11
7 12
8 13
9 14
10 15
11 16
12 17
13 18
14 19
15 20
16 21
17 -
18 -
19 22
20 23
21 24
22 25
23 26
24 27
25 28
26 29
27 30
28 31
29 32
30 33
31 34
32 35
33 36
DRQFN Pin# VFBGA Pin# PAD EXTINT PCINT ADC/AC OSC T/C # 0 T/C # 1 USART I2C SPI JTAG
A1 B2
B1 B1
A2 C3
B2 C2
A3 A5
B3 A1
A4 D2
B4 E1
A5 D3
B5 E2
A6 F1
A7 F2
B6 G2
A8 E3
B7 F3
A9 E4
B8 C1
A10 A4
B9 F4
A11 G5
B10 F5
A12 G6
A13 F6
B11 E5
A14 F7
B12 E6
A15 E7
B13 D1
A16 C7
B14 D6
A17 C6
B15 B7
A18 D5
PB[5]
PB[6]
PB[7]
RESET
VCC
GND
XTAL2
XTAL1
PD[0]
PD[1]
PD[2] INT0
PD[3] INT1
PD[4]
PD[5]
PD[6]
PD[7]
VCC
GND
PC[0]
PC[1]
PC[2]
PC[3]
PC[4]
PC[5]
PC[6]
PC[7]
AVCC
GND
AREF
PA[7]
PA[6]
PA[5]
PA[4]
PCINT13
PCINT14
PCINT15
PCINT24
PCINT25
PCINT26
PCINT27
PCINT28
PCINT29
PCINT30
PCINT31
PCINT16
PCINT17
PCINT18
PCINT19
PCINT20
PCINT21
PCINT22
PCINT23
AREF
PCINT7 ADC7
PCINT6 ADC6
PCINT5 ADC5
PCINT4 ADC4
MOSI
MISO
SCK
RxD0
TxD0
RxD1
TXD1
OC1B XCK1
OC1A
OC2B ICP1
OC2A
RxD2
TxD2
TOSC1
TOSC2
MISO1
MOSI1
SCL
SDA
TCK
TMS
TDO
TDI
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32-pin
40-pin
TQFP/ QFN/ PIPD Pin
MLF Pin # #
34 37
35 38
36 39
37 40
38 -
39 -
40 1
41 2
42 3
43 4
44 5
--
--
--
--
--
DRQFN Pin# VFBGA Pin# PAD
A19 B6
B16 A6
A20 C5
B17 B5
A21 G3
B18 A7
A22 B4
B19 C4
A23 A3
B20 B3
A24 A2
- D4
- D7
- G1
- G4
- G7
PA[3]
PA[2]
PA[1]
PA[0]
VCC
GND
PB[0]
PB[1]
PB[2]
PB[3]
PB[4]
GND
GND
GND
GND
GND
EXTINT PCINT ADC/AC OSC T/C # 0 T/C # 1 USART I2C SPI
PCINT3 ADC3
PCINT2 ADC2
PCINT1 ADC1
PCINT0 ADC0
INT2
PCINT8
PCINT9
PCINT10 AIN0
PCINT11 AIN1
PCINT12
T0
CLKO
T1
OC0A
OC0B
XCK0
SDA1
SCL1
SS
JTAG
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7. General Information
7.1.
Resources
A comprehensive set of development tools, application notes, and datasheets are available for download
on http://www.atmel.com/avr.
7.2.
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C or 100 years at 25°C.
7.3.
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compilation. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C
is compiler dependent. Confirm with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions
must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”
combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
7.4. Capacitive Touch Sensing
7.4.1.
QTouch Library
The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on
most Atmel AVR® microcontrollers. The QTouch Library includes support for the Atmel QTouch and Atmel
QMatrix® acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the
AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors,
and then calling the touch sensing API’s to retrieve the channel information and determine the touch
sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location: http://
www.atmel.com/technologies/touch/. For implementation details and other information, refer to the Atmel
QTouch Library User Guide - also available for download from the Atmel website.
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8. AVR CPU Core
8.1.
Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must therefore be able to access memories, perform
calculations, control peripherals, and handle interrupts.
Figure 8-1. Block Diagram of the AVR Architecture
Register file
R31 (ZH)
R29 (YH)
R27 (XH)
R25
R23
R21
R30 (ZL)
R28 (YL)
R26 (XL)
R24
R22
R20
R19 R18
R17 R16
R15 R14
R13 R12
R11 R10
R9 R8
R7 R6
R5 R4
R3 R2
R1 R0
Program
counter
Flash program
memory
Instruction
register
Instruction
decode
Stack
pointer
Status
register
ALU
Data memory
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the Register File, the operation is executed, and the result is
stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space
addressing – enabling efficient address calculations. One of the these address pointers can also be used
as an address pointer for look up tables in Flash program memory. These added function registers are
the 16-bit X-, Y-, and Z-register, described later in this section.
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The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic operation, the
Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly
address the whole address space. Most AVR instructions have a single 16-bit word format. Every
program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application
Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.
The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only
limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the
Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write
accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt
Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector
table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the
Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI,
and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations
following those of the Register File, 0x20 - 0x5F. In addition, this device has Extended I/O space from
0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
8.2.
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working
registers. Within a single clock cycle, arithmetic operations between general purpose registers or between
a register and an immediate are executed. The ALU operations are divided into three main categories –
arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful
multiplier supporting both signed/unsigned multiplication and fractional format. See Instruction Set
Summary section for a detailed description.
Related Links
Instruction Set Summary on page 462
8.3.
Status Register
The Status Register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. The Status Register is updated after all ALU operations, as specified in the Instruction Set
Reference. This will in many cases remove the need for using the dedicated compare instructions,
resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when
returning from an interrupt. This must be handled by software.
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8.3.1.
Status Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name:  SREG
Offset:  0x5F
Reset:  0x00
Property: When addressing as I/O Register: address offset is 0x3F
 
Bit 7 6 5 4 3 2 1 0
I THSVNZC
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable Register is
cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-
bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI
instructions, as described in the instruction set reference.
Bit 6 – T: Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for
the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and
a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.
Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Flag is useful in
BCD arithmetic. See the Instruction Set Description for detailed information.
Bit 4 – S: Sign Flag, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow
Flag V. See the Instruction Set Description for detailed information.
Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the Instruction Set
Description for detailed information.
Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
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Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description
for detailed information.
8.4.
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the
required performance and flexibility, the following input/output schemes are supported by the Register
File:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 8-2. AVR CPU General Purpose Working Registers
70
Addr.
Ge n e ra l
P urpos e
R0 0x00
R1 0x01
R2 0x02
R13 0x0D
R14 0x0E
R15 0x0F
Working
Re gis te rs
R16 0x10
R17 0x11
R26
0x1A
X-re gis te r Low Byte
R27
0x1B
X-re gis te r High Byte
R28
0x1C
Y-re gis te r Low Byte
R29
0x1D
Y-re gis te r High Byte
R30
0x1E
Z-re gis te r Low Byte
R31
0x1F
Z-re gis te r High Byte
Most of the instructions operating on the Register File have direct access to all registers, and most of
them are single cycle instructions. As shown in the figure, each register is also assigned a data memory
address, mapping them directly into the first 32 locations of the user Data Space. Although not being
physically implemented as SRAM locations, this memory organization provides great flexibility in access
of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.
8.4.1.
The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage. These registers are
16-bit address pointers for indirect addressing of the data space. The three indirect address registers X,
Y, and Z are defined as described in the figure.
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Figure 8-3. The X-, Y-, and Z-registers
15 XH
XL 0
X-register
7
07
0
R27
15 YH
R26
YL 0
Y-register
7
07
0
R29 R28
15 ZH
ZL 0
Z-register
7
07
0
R31 R30
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
Related Links
Instruction Set Summary on page 462
8.5.
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return
addresses after interrupts and subroutine calls. The Stack is implemented as growing from higher to
lower memory locations. The Stack Pointer Register always points to the top of the Stack.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are
located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be
defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack
Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point
above start of the SRAM. See the table for Stack Pointer details.
Table 8-1. Stack Pointer Instructions
Instruction Stack pointer
Description
PUSH
Decremented by 1 Data is pushed onto the stack
CALL
ICALL
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
interrupt
RCALL
POP
RET
RETI
Incremented by 1 Data is popped from the stack
Incremented by 2 Return address is popped from the stack with return from subroutine or
return from interrupt
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
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8.5.1.
Stack Pointer Register Low and High byte
The SPL and SPH register pair represents the 16-bit value, SP.The low byte [7:0] (suffix L) is accessible
at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on
reading and writing 16-bit registers, refer to Accessing 16-bit Registers.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 locations reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name:  SPL and SPH
Offset:  0x5D
Reset:  0x10FF
Property: When addressing I/O Registers as data space the offset address is 0x3D
 
Bit
Access
Reset
15
R
0
14 13 12 11 10
9
8
SP13
SP12
SP11
SP10
SP9
SP8
R RW RW RW RW RW RW
0100000
Bit 7 6 5 4 3 2 1 0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Reset
1
1
1
1
1
1
1
1
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 – SPn: Stack Pointer Register
SPL and SPH are combined into SP.
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8.5.2.
Extended Z-pointer Register for ELPM/SPM
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 locations reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name:  RAMPZ
Offset:  0x5B
Reset:  0x0
Property: When addressing I/O Registers as data space the offset address is 0x3B
 
Bit 7 6 5 4 3 2 1 0
RAMPZ[7:0]
Access
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
Bits 7:0 – RAMPZ[7:0]: Extended Z-pointer Register for ELPM/SPM
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in the
below figure. Note that LPM is not affected by the RAMPZ setting.
Figure 8-4. The Z-pointer used by ELPM and SPM
Bit (Individually)
7
07
07
0
RAMPZ
ZH ZL
Bit (Z-pointer)
23
16 15
87
0
The actual number of bits is implementation dependent. Unused bits in an implementation will always
read as zero. For compatibility with future devices, be sure to write these bits to zero.
8.6.
Accessing 16-bit Registers
The AVR data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations. These
registers must be byte-accessed using two read or write operations. 16-bit registers are connected to the
8-bit bus and a temporary register using a 16-bit bus.
For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte
is then written into the temporary register. When the high byte of the 16-bit register is written, the
temporary register is copied into the low byte of the 16-bit register in the same clock cycle.
For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low
byte register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register
in the same clock cycle as the low byte is read. When the high byte is read, it is then read from the
temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when
reading or writing the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit
register during an atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when
writing or reading 16-bit registers.
The temporary registers can also be read and written directly from user software.
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8.7.
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is
driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal
clock division is used. The Figure below shows the parallel instruction fetches and instruction executions
enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 8-5. The Parallel Instruction Fetches and Instruction Executions
T1 T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
The following Figure shows the internal timing concept for the Register File. In a single clock cycle an
ALU operation using two register operands is executed, and the result is stored back to the destination
register.
Figure 8-6. Single Cycle ALU Operation
T1
T2 T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
8.8.
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector
each have a separate program vector in the program memory space. All interrupts are assigned individual
enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status
Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be
automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt
Vectors. They have determined priority levels: The lower the address the higher is the priority level.
RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors
can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register
(MCUCR). The Reset Vector can also be moved to the start of the Boot Flash section by programming
the BOOTRST Fuse.
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When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt
instruction – RETI – is executed.
There are basically two types of interrupts:
The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program
Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and
hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic
one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding
interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled,
or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global
Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do
not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled,
the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main
program and execute one more instruction before any pending interrupt is served.
The Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No
interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.
The following example shows how this can be used to avoid interrupts during the timed EEPROM write
sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
Note:  Please refer to About Code Examples.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before
any pending interrupts, as shown in this example.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
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8.8.1.
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
Note:  Please refer to About Code Examples.
Related Links
Memory Programming on page 387
Boot Loader Support – Read-While-Write Self-Programming on page 370
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After
four clock cycles the program vector address for the actual interrupt handling routine is executed. During
this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump
to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a
multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs
when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles.
This increase comes in addition to the start-up time from the selected sleep mode. A return from an
interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter
(two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG
is set.
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9. AVR Memories
9.1.
Overview
This section describes the different memory types in the device. The AVR architecture has two main
memory spaces, the Data Memory and the Program Memory space. In addition, the device features an
EEPROM Memory for data storage. All memory spaces are linear and regular.
9.2.
In-System Reprogrammable Flash Program Memory
The ATmega1284 contains 128Kbytes On-chip In-System Reprogrammable Flash memory for program
storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 64 x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega1284 Program
Counter (PC) is 16 bits wide, thus addressing the 64 program memory locations. The operation of Boot
Program section and associated Boot Lock bits for software protection are described in detail in Boot
Loader Support – Read-While-Write Self-Programming. Refer to Memory Programming for the description
on Flash data serial downloading using the SPI pins or the JTAG interface.
Constant tables can be allocated within the entire program memory address space, using the Load
Program Memory (LPM) instruction.
Timing diagrams for instruction fetch and execution are presented in Instruction Exectution Timing.
Figure 9-1. Program Memory Map ATmega1284
Program Memory
0x0000
Application Flash Section
Boot Flash Section
0xFFFF
Related Links
BTLDR - Boot Loader Support – Read-While-Write Self-Programming on page 370
MEMPROG- Memory Programming on page 387
Instruction Execution Timing on page 26
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9.3.
SRAM Data Memory
The following figure shows how the device SRAM Memory is organized.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60
- 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
The lower 4352 data memory locations address both the Register File, the I/O memory, Extended I/O
memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64
location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 4096
locations address the internal data SRAM.
The five different addressing modes for the data memory cover:
Direct
The direct addressing reaches the entire data space.
Indirect with Displacement
The Indirect with Displacement mode reaches 63 address locations from the base address
given by the Y- or Z-register.
Indirect
In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
Indirect with Pre-decrement
The address registers X, Y, and Z are decremented.
Indirect with Post-increment
The address registers X, Y, and Z are incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 16K
bytes of internal data SRAM in the device are all accessible through all these addressing modes.
Figure 9-2. Data Memory Map with 16384 byte internal data SRAM
(16384x8)
0x40FF
9.3.1.
Data Memory Access Times
The internal data SRAM access is performed in two clkCPU cycles as described in the following Figure.
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