ON Semiconductor Electronic Components Datasheet  


74HC14

Hex Schmitt-Trigger Inverter


74HC14 Datasheet PDF
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74HC14
Hex Schmitt−Trigger
Inverter
HighPerformance SiliconGate CMOS
The 74HC14 is identical in pinout to the LS14, LS04 and the HC04.
The device inputs are compatible with Standard CMOS outputs; with
pullup resistors, they are compatible with LSTTL outputs.
The HC14 is useful to “square up” slow input rise and fall times.
Due to hysteresis voltage of the Schmitt trigger, the HC14 finds
applications in noisy environments.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 60 FETs or 15 Equivalent Gates
These are PbFree Devices
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MARKING
DIAGRAMS
14
1
14
SOIC14
D SUFFIX
CASE 751A
1
HC14G
AWLYWW
14
1
TSSOP14
DT SUFFIX
CASE 948G
14
HC
14
ALYW G
1G
HC14 = Device Code
A = Assembly Location
L, WL = Wafer Lot
Y = Year
W, WW = Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 Rev. 1
1
Publication Order Number:
74HC14/D


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74HC14
Pinout: 14Lead Packages (Top View)
VCC A6 Y6 A5 Y5 A4 Y4
14 13 12 11 10 9 8
1234567
A1 Y1 A2 Y2 A3 Y3 GND
FUNCTION TABLE
Inputs
Outputs
AY
LH
HL
LOGIC DIAGRAM
1
A1
2
Y1
3
A2
4
Y2
5
A3
9
A4
11
A5
6
Y3
Y=A
8
Y4 Pin 14 = VCC
Pin 7 = GND
10
Y5
13
A6
12
Y6
ORDERING INFORMATION
Device
Package
Shipping
74HC14DR2G
SOIC14
(PbFree)
2500 / Tape & Reel
74HC14DTR2G
TSSOP14*
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently PbFree.
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74HC14 Datasheet PDF
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74HC14
ÎÎMÎÎSAymXÎÎbIMolUÎÎM RÎÎATÎÎINGÎÎS ÎÎÎÎPaÎÎramÎÎeterÎÎÎÎÎÎÎÎÎÎÎÎÎÎVÎÎalueÎÎÎÎÎÎUniÎÎt
VCC DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
Vin DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5 V
Vout DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5 V
Iin DC Input Current, per Pin
±20 mA
Iout DC Output Current, per Pin
±25 mA
ICC DC Supply Current, VCC and GND Pins
±50 mA
PD Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
mW
Tstg Storage Temperature Range
– 65 to + 150
TL Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
260
_C
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not im-
plied. Extended exposure to stresses above the Recommended Operating Conditions may af-
fect device reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Vin, Vout
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to
GND)
TA Operating Temperature Range, All Package Types
tr, tf Input Rise/Fall Time
(Figure 1)
*When Vin = 50% VCC, ICC > 1mA
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
2.0
0
– 55
0
0
0
Max
6.0
VCC
+ 125
No Limit*
No Limit*
No Limit*
Unit
V
V
_C
ns
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74HC14
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
VCC Guaranteed Limit
(V) 55 to 25°C 85°C 125°C Unit
VT+ max
Maximum PositiveGoing Input
Threshold Voltage
(Figure 3)
Vout = 0.1V
|Iout| 20mA
2.0
1.50
1.50 1.50
V
3.0 2.15 2.15 2.15
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VT+ min
Minimum PositiveGoing Input
Threshold Voltage
(Figure 3)
Vout = 0.1V
|Iout| 20mA
2.0
1.0
0.95 0.95
V
3.0 1.5 1.45 1.45
4.5 2.3 2.25 2.25
6.0 3.0 2.95 2.95
VTmax
Maximum NegativeGoing Input
Threshold Voltage
(Figure 3)
Vout = VCC 0.1V
|Iout| 20mA
2.0
0.9
0.95 0.95
V
3.0 1.4 1.45 1.45
4.5 2.0 2.05 2.05
6.0 2.6 2.65 2.65
VTmin
Minimum NegativeGoing Input
Threshold Voltage
(Figure 3)
Vout = VCC 0.1V
|Iout| 20mA
2.0 0.3
3.0 0.5
4.5 0.9
6.0 1.2
0.3 0.3 V
0.5 0.5
0.9 0.9
1.2 1.2
VHmax
Note 2
Maximum Hysteresis Voltage
(Figure 3)
Vout = 0.1V or VCC 0.1V
|Iout| 20mA
2.0
1.20
1.20 1.20
V
3.0 1.65 1.65 1.65
4.5 2.25 2.25 2.25
6.0 3.00 3.00 3.00
VHmin
Note 2
Minimum Hysteresis Voltage
(Figure 3)
Vout = 0.1V or VCC 0.1V
|Iout| 20mA
2.0
0.20
0.20 0.20
V
3.0 0.25 0.25 0.25
4.5 0.40 0.40 0.40
6.0 0.50 0.50 0.50
VOH
Minimum HighLevel Output
Voltage
Vin VTmin
|Iout| 20mA
2.0 1.9
4.5 4.4
6.0 5.9
1.9 1.9 V
4.4 4.4
5.9 5.9
Vin VTmin
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
3.0
4.5
6.0
VOL Maximum LowLevel Output Vin VT+ max
Voltage
|Iout| 20mA
2.0
4.5
6.0
2.48
3.98
5.48
0.1
0.1
0.1
2.34 2.20
3.84 3.70
5.34 5.20
0.1 0.1
0.1 0.1
0.1 0.1
V
Iin Maximum Input Leakage
Current
Vin VT+ max
Vin = VCC or GND
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
3.0
4.5
6.0
6.0
0.26
0.26
0.26
±0.1
0.33 0.40
0.33 0.40
0.33 0.40
±1.0 ±1.0 mA
ICC Maximum Quiescent Supply Vin = VCC or GND
Current (per Package)
Iout = 0mA
6.0 2.0
20 40 mA
1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the ON
Semiconductor HighSpeed CMOS Data Book (DL129/D).
2. VHmin > (VT+ min) (VTmax); VHmax = (VT+ max) (VTmin).
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74HC14
AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)
Symbol
Parameter
VCC Guaranteed Limit
(V) 55 to 25°C 85°C
125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0 75
3.0 30
4.5 15
6.0 13
95 110 ns
40 55
19 22
16 19
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0 75
3.0 27
4.5 15
6.0 13
95 110 ns
32 36
19 22
16 19
Cin Maximum Input Capacitance
10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor HighSpeed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Inverter)*
22 pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
tf tr
INPUT A
90%
50%
10%
OUTPUT Y
tPLH
90%
50%
10%
tTLH
tPHL
Figure 1. Switching Waveforms
VCC
GND
tTHL
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 2. Test Circuit
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74HC14
4
3
(VT+)
VHtyp
2
(VT−)
1
23456
VCC, POWER SUPPLY VOLTAGE (VOLTS)
VHtyp = (VT+ typ) − (VT− typ)
Figure 3. Typical Input Threshold, VT+, VTversus Power Supply Voltage
A
(a) A Schmitt−Trigger Squares Up Inputs With Slow Rise and Fall Times
VH
Vin
VCC
VT+
VT−
GND
VOH
Vout
VOL
Y
(b) A Schmitt−Trigger Offers Maximum Noise Immunity
VH
Vin
VCC
VT+
VT−
GND
VOH
Vout
VOL
Figure 4. Typical SchmittTrigger Applications
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74HC14
PACKAGE DIMENSIONS
SOIC14
CASE 751A03
ISSUE H
14
1
T
SEATING
PLANE
A
G
8
BP 7 PL
0.25 (0.010) M B M
7
C R X 45 _
F
D 14 PL
K
0.25 (0.010) M T B S A S
M
J
SOLDERING FOOTPRINT*
14X
0.58
7X
7.04
1
14X
1.52
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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74HC14
PACKAGE DIMENSIONS
TSSOP14
CASE 948G01
ISSUE B
0.15 (0.006) T U S
2X L/2 14
L
PIN 1
IDENT.
1
14X K REF
0.10 (0.004) M T U S V S
N
8
B
UN
0.25 (0.010)
M
F
7 DETAIL E
0.15 (0.006) T U S
A
V
ÇÇÇÉÉÇÇÇÉÉÇÇÇÉÉJ J1
K
K1
SECTION NN
0.10 (0.004)
TSEATING
PLANE
D
C
G
H DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.
W
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC
0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
M 0_ 8_ 0_ 8_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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74HC14
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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For additional information, please contact your local
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74HC14/D




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