FDML7610S Datasheet PDF
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FDML7610S
PowerTrench® Power Stage
Asymmetric Dual N-Channel MOSFET
Features
Q1: N-Channel
„ Max rDS(on) = 7.5 mΩ at VGS = 10 V, ID = 12 A
„ Max rDS(on) = 12 mΩ at VGS = 4.5 V, ID = 10 A
Q2: N-Channel
„ Max rDS(on) = 4.2 mΩ at VGS = 10 V, ID = 17 A
„ Max rDS(on) = 5.5 mΩ at VGS = 4.5 V, ID = 14 A
„ RoHS Compliant
April 2013
General Description
This device includes two specialized N-Channel MOSFETs in a
dual MLP package.The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
efficiency.
Applications
„ Computing
„ Communications
„ General Purpose Point of Load
„ Notebook VCORE
Pin 1
D1 D1 D1
G1
D1
PHASE
(S1/D2)
S2 5
S2 6
Q2
PHASE
4 D1
3 D1
G2S2 S2S2
S2 7
G2 8
2 D1
Q1 1 G1
Top
MLP 3X4.5
Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
PD
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
Power Dissipation for Single Operation
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 3)
TC = 25 °C
TC = 25 °C
TA = 25 °C
TA = 25 °C
TA = 25 °C
Q1 Q2
30 30
±20 ±20
30 28
40
121a
60
171b
40
2.11a
0.81c
40
2.21b
0.91d
-55 to +150
Units
V
V
A
W
°C
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
601a
1501c
4
561b
1401d
3.5
°C/W
Device Marking
FDML7610S
Device
FDML7610S
Package
MLP3X4.5
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
1
www.fairchildsemi.com

Total : 15 Pages
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