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dsPIC33FJ128GP306A Datasheet

Part Number dsPIC33FJ128GP306A
Manufacturers Microchip
Logo Microchip
Description 16-bit Digital Signal Controllers
Datasheet dsPIC33FJ128GP306A DatasheetdsPIC33FJ128GP306A Datasheet (PDF)

dsPIC33FJXXXGPX06A/X08A/X10A 16-bit Digital Signal Controllers (up to 256 KB Flash and 30 KB SRAM) with Advanced Analog Operating Conditions • 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS • 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS Timers/Output Compare/Input Capture • Up to nine 16-bit timers/counters. Can pair up to make four 32-bit timers. • Eight Output Compare modules configurable as timers/counters • Eight Input Capture modules Core: 16-bit dsPIC33F CPU • • • • Code-efficient (C and A.

  dsPIC33FJ128GP306A   dsPIC33FJ128GP306A






Part Number dsPIC33FJ128GP306
Manufacturers Microchip Technology
Logo Microchip Technology
Description 16-Bit Digital Signal Controller
Datasheet dsPIC33FJ128GP306A DatasheetdsPIC33FJ128GP306 Datasheet (PDF)

dsPIC33FJXXXGPX06/X08/X10 Data Sheet High-Performance, 16-Bit Digital Signal Controllers © 2009 Microchip Technology Inc. DS70286C Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are.

  dsPIC33FJ128GP306A   dsPIC33FJ128GP306A







16-bit Digital Signal Controllers

dsPIC33FJXXXGPX06A/X08A/X10A 16-bit Digital Signal Controllers (up to 256 KB Flash and 30 KB SRAM) with Advanced Analog Operating Conditions • 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS • 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS Timers/Output Compare/Input Capture • Up to nine 16-bit timers/counters. Can pair up to make four 32-bit timers. • Eight Output Compare modules configurable as timers/counters • Eight Input Capture modules Core: 16-bit dsPIC33F CPU • • • • Code-efficient (C and Assembly) architecture Two 40-bit wide accumulators Single-cycle (MAC/MPY) with dual data fetch Single-cycle mixed-sign MUL plus hardware divide Communication Interfaces • Two UART modules (10 Mbps) - With support for LIN 2.0 protocols and IrDA® • Two 4-wire SPI modules (15 Mbps) • Up to two I2C™ modules (up to 1 Mbaud) with SMBus support • Up to two Enhanced CAN (ECAN) modules (1 Mbaud) with 2.0B support • Data Converter Interface (DCI) module with I2S codec support Clock Management • • • • • ±2% internal oscillator Programmable PLLs and oscillator clock sources Fail-Safe Clock Monitor (FSCM) Independent Watchdog Timer (WDT) Fast wake-up and start-up Power Management • Low-power management modes (Sleep, Idle, Doze) • Integrated Power-on Reset and Brown-out Reset • 2.1 mA/MHz dynamic current (typical) • 50 μA IPD current (typical) Input/Output • Sink/Source up to 10 mA (pin specific) for standard VOH/VOL, up to 16 mA (pin specific) for non-standard VOH1 • 5V-tolerant pins • Selectab.


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