ZL50018

www.DataSheet4U.com ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL Data Sheet Features 2048 channel x 2048 channel non-blocking digital Time Division Multiplex (TDM) switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or 16.384 Mbps 32 serial TDM input, 32 serial TDM output streams Integrated Digital Phase-Locked Loop (DPLL) exceeds Telcordia GR-1244-CORE Stratum 3 specifications Output clocks have less than 1 ns of jitter (except for the 1.544 MHz output) DPLL provides holdover, freerun and jitter attenuation features with four independent reference source inputs Ordering Information ZL50018GAC ZL50018QCC 256 Ball PBGA 256 Lead LQFP Trays Trays July 2005 -40° C to +85 ° C Programmable key DPLL parameters (filter corner frequency, locking range, auto-holdover hysteresis range, phase slope, lock detector range) Exceptional input clock cycle to cycle variation tolerance (20 ns for all rates) Output streams can be configured as bidirectional for connection to backplanes VDD_CORE VDD_IO VDD_COREA VDD_IOA VSS RESET ODE STi[31:0] FPi CKi MODE_4M0 MODE_4M1 REF0 REF1 REF2 REF3 REF_FAIL0 REF_FAIL1 REF_FAIL2 REF_FAIL3 S/P Converter Data Memory P/S Converter STio[31:0] Input Timing Connection Memory Output HiZ Control STOHZ[15:0] DPLL Output Timing FPo[3:0] CKo[5:0] FPo_OFF[2:0] OSC_EN OSC Internal Registers & Microprocessor Interface Test Port TDi OSCo DS_RD R/W_WR Figure 1 - ZL50018...