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X17256128DD8M Datasheet

Part Number X17256128DD8M
Manufacturers Xilinx Inc
Logo Xilinx  Inc
Description QPRO Family of XC1700D QML Configuration PROMs
Datasheet X17256128DD8M DatasheetX17256128DD8M Datasheet (PDF)

0 R QPRO Family of XC1700D QML Configuration PROMs 0 2 DS070 (v2.1) June 1, 2000 Product Specification Features • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices On-chip address counter, incremented by each rising edge on the clock input .

  X17256128DD8M   X17256128DD8M






Part Number X17256128DD8B
Manufacturers Xilinx Inc
Logo Xilinx  Inc
Description QPRO Family of XC1700D QML Configuration PROMs
Datasheet X17256128DD8M DatasheetX17256128DD8B Datasheet (PDF)

0 R QPRO Family of XC1700D QML Configuration PROMs 0 2 DS070 (v2.1) June 1, 2000 Product Specification Features • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices On-chip address counter, incremented by each rising edge on the clock input .

  X17256128DD8M   X17256128DD8M







QPRO Family of XC1700D QML Configuration PROMs

0 R QPRO Family of XC1700D QML Configuration PROMs 0 2 DS070 (v2.1) June 1, 2000 Product Specification Features • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices On-chip address counter, incremented by each rising edge on the clock input Simple interface to the FPGA requires only one user I/O pin Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions Low-power CMOS EPROM process Available in 5V version only Programming support by leading programmer manufacturers. Design support using the Xilinx Alliance and Foundation series software packages. Description The XC1700D QPRO™ family of configuration PROMs provide an easy-to-use, cost-effective method for storing Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA D IN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be .


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