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VT83205S1 Datasheet

Part Number VT83205S1
Manufacturers Vaishali Semiconductor
Logo Vaishali Semiconductor
Description 3.3V Low Phase Noise VCXO Voltage-Controlled Crystal Oscillator and PLL Clock Synthesizer
Datasheet VT83205S1 DatasheetVT83205S1 Datasheet (PDF)

VT83205 3.3V Low Phase Noise VCXO (Voltage-Controlled Crystal Oscillator) and PLL Clock Synthesizer Applications •= •= Telecom switching Set-top boxes •= •= HDTV MPEG Video clock source General Description The Vaishali VT83205 is a single-chip, integrated VCXO and Phase Locked Loop (PLL) clock synthesizer. The device uses the VCXO and an analog Phase-Locked Loop (PLL) to accept a 10 MHz to 14.318 MHz, 30pF (pull range of 200 ppm) crystal input, in order to produce either one or two output clock.

  VT83205S1   VT83205S1






Part Number VT83205S1X
Manufacturers Vaishali Semiconductor
Logo Vaishali Semiconductor
Description 3.3V Low Phase Noise VCXO Voltage-Controlled Crystal Oscillator and PLL Clock Synthesizer
Datasheet VT83205S1 DatasheetVT83205S1X Datasheet (PDF)

VT83205 3.3V Low Phase Noise VCXO (Voltage-Controlled Crystal Oscillator) and PLL Clock Synthesizer Applications •= •= Telecom switching Set-top boxes •= •= HDTV MPEG Video clock source General Description The Vaishali VT83205 is a single-chip, integrated VCXO and Phase Locked Loop (PLL) clock synthesizer. The device uses the VCXO and an analog Phase-Locked Loop (PLL) to accept a 10 MHz to 14.318 MHz, 30pF (pull range of 200 ppm) crystal input, in order to produce either one or two output clock.

  VT83205S1   VT83205S1







3.3V Low Phase Noise VCXO Voltage-Controlled Crystal Oscillator and PLL Clock Synthesizer

VT83205 3.3V Low Phase Noise VCXO (Voltage-Controlled Crystal Oscillator) and PLL Clock Synthesizer Applications •= •= Telecom switching Set-top boxes •= •= HDTV MPEG Video clock source General Description The Vaishali VT83205 is a single-chip, integrated VCXO and Phase Locked Loop (PLL) clock synthesizer. The device uses the VCXO and an analog Phase-Locked Loop (PLL) to accept a 10 MHz to 14.318 MHz, 30pF (pull range of 200 ppm) crystal input, in order to produce either one or two output clocks. A 0 to 3V control signal is used to fine tune the output clock frequency in the ±100ppm range. Select inputs SO:S2 are used for frequency and output selection. Features •= •= •= •= 3.3V supply operation Packaged in 16-pin SOIC & QSOP packages. Replaces separate VCXO and multiplier Uses inexpensive pullable crystal •= •= •= On-chip VCXO with 200 ppm pull range (±100 ppm) 5V-tolerant control inputs Zero ppm synthesis error in both clocks Figure 1. Functional Block Diagram VDD1 VDD2 VIN X2 Load Cap Control Output Buffer osc Low Phase Noise PLL Output Buffer X1 S2:S0 OE CLK2 CLK1 10-14 MHz Pullable Crystal Load Caps 2001-03-08 Vaishali Semiconductor Page 1 www.vaishali.com 1300 White Oaks Road, Ste. 200 Campbell MDST-0001-01 CA 95008 Ph. 408.377.6060 Fax 408.377.6063 VT83205 Figure 2. Pin Configuration VT83205 Pinout X1 VDD1 VDD1 VIN GND GND S2 OE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 NC S1 GND CLK2 VDD2 S0 CLK1 Table 1. Pin Description Name X1 VDD1 VIN GND S2 OE CLK1 .


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