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USB97C100 Datasheet

Part Number USB97C100
Manufacturers SMSC Corporation
Logo SMSC Corporation
Description Multi-Endpoint USB Peripheral Controller
Datasheet USB97C100 DatasheetUSB97C100 Datasheet (PDF)

USB97C100 ADVANCE INFORMATION Multi-Endpoint USB Peripheral Controller FEATURES High Performance USB Peripheral Controller Engine Integrated USB Transceiver Serial Interface Engine (SIE) 8051 Microcontroller (MCU) Patented Memory Management Unit (MMU) 4 Channel 8237 DMA Controller (ISADMA) 4K Byte On Board USB Packet Buffer Quasi-ISA Peripheral Interface USB Bus Snooping Capabilities GPIOs Complete USB Specification 1.1 Compatibility Isochronous, Bulk, Interrupt, and Control Data Independently .

  USB97C100   USB97C100






Part Number USB97C102
Manufacturers SMSC Corporation
Logo SMSC Corporation
Description Multi-Endpoint USB Peripheral Controller
Datasheet USB97C100 DatasheetUSB97C102 Datasheet (PDF)

USB97C102 Multi-Endpoint USB Peripheral Controller with Integrated 5 Port HUB FEATURES !" High Performance USB Peripheral Controller Engine Integrated USB Transceiver Serial Interface Engine (SIE) 8051 Microcontroller (MCU) Patented Memory Management Unit (MMU) 4 Channel 8237 DMA Controller (ISADMA) 4K Byte On Board USB Packet Buffer Quasi-ISA Peripheral Interface USB Bus Snooping Capabilities GPIOs !" Pin Compatible with SMSC USB97C100 !" Complete USB Specification 1.1 Compatibility Isochronou.

  USB97C100   USB97C100







Multi-Endpoint USB Peripheral Controller

USB97C100 ADVANCE INFORMATION Multi-Endpoint USB Peripheral Controller FEATURES High Performance USB Peripheral Controller Engine Integrated USB Transceiver Serial Interface Engine (SIE) 8051 Microcontroller (MCU) Patented Memory Management Unit (MMU) 4 Channel 8237 DMA Controller (ISADMA) 4K Byte On Board USB Packet Buffer Quasi-ISA Peripheral Interface USB Bus Snooping Capabilities GPIOs Complete USB Specification 1.1 Compatibility Isochronous, Bulk, Interrupt, and Control Data Independently Configurable per Endpoint Dynamic Hardware Allocation of -Packet Buffer for Virtual Endpoints Multiple Virtual Endpoints (up to 16 TX, 16 RX Simultaneously) Multiple Alternate Address Filters Dynamic Endpoint Buffer Length Allocation (0-1280 Byte Packets) High Speed (12Mbps) Capability MMU and SRAM Buffer Allow Buffer Optimization and Maximum Utilization of USB Bandwidth 128 Byte Page Size 10 Pages Maximum per Packet Up to 16 Deep Receive Packet Queue Up to 5 Deep Transmit Packet Queue, per Endpoint Hardware Generated Packet Header Records Each Packet Status Automatically Simultaneous Arbitration Between MCU, SIE, and ISA DMA Accesses Extended Power Management Standard 8051 "Stop Clock" Modes Additional USB and ISA Suspend Resume Events Internal 8MHz Ring Oscillator for Immediate Low Power Code Execution 24, 16, 12, 8, 4, and 2 MHz PLL Taps For on the Fly MCU and DMA Clock Switching Independent Clock/Power Management for SIE, MMU, DMA and MCU DMA Capability with ISA Memory Four Indepen.


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