NEC's 3 V DUAL DOWNCONVERTER AND UPB1007K PLL FREQUENCY SYNTHESIZER
FEATURES
• INTEGRATED RF BLOCK: LNA, RF & IF Downconverter + PLL frequency synthesizer • STATE OF THE ART 25 GHz fT UHS0 BIPOLAR PROCESS • DOUBLE-CONVERSION: f1stIF = 61.380 MHz f2ndIF = 4.092 MHz • ADJUSTABLE GAIN: 20 dB range MIN • FIXED DIVISION PRESCALER • LOW POWER CONSUMPTION: 25 mA @ 3 V • SMALL 36 PIN QFN PACKAGE Flat lead style for better performance • TAPE AND REEL PACKAGING AVAILABLE
DESCRIPTION
NEC's UPB1007K is a S.
PLL FREQUENCY SYNTHESIZER
NEC's 3 V DUAL DOWNCONVERTER AND UPB1007K PLL FREQUENCY SYNTHESIZER
FEATURES
• INTEGRATED RF BLOCK: LNA, RF & IF Downconverter + PLL frequency synthesizer • STATE OF THE ART 25 GHz fT UHS0 BIPOLAR PROCESS • DOUBLE-CONVERSION: f1stIF = 61.380 MHz f2ndIF = 4.092 MHz • ADJUSTABLE GAIN: 20 dB range MIN • FIXED DIVISION PRESCALER • LOW POWER CONSUMPTION: 25 mA @ 3 V • SMALL 36 PIN QFN PACKAGE Flat lead style for better performance • TAPE AND REEL PACKAGING AVAILABLE
DESCRIPTION
NEC's UPB1007K is a Silicon RFIC designed for low cost GPS receivers. The IC combines an LNA, followed by a doubleconversion RF/IF downconverter block and a PLL frequency synthesizer on one chip. The device operates on a 3V supply voltage and is housed in a small 36 pin QFN (Quad Flat Nolead) package, resulting in low power consumption and reduced board space. The device is manufactured using the state of the art UHS0 25 GHz fT silicon bipolar process. NEC's stringent quality assurance and test procedures ensure the highest reliability and performance.
APPLICATIONS
• LOW POWER HANDHELD GPS RECEIVER • IN-VEHICLE NAVIGATION SYSTEMS • PC/PDA+GPS INTEGRATION
ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 3.0 V, unless otherwise specified)
SYMBOLS ICC VCC PART NUMBER PACKAGE OUTLINE PARAMETERS AND CONDITIONS Total Circuit Current, No Signals Supply Voltage UNITS mA V 2.7 MIN UPB1007K QFN-36 TYP 25 3.0 MAX 31 3.3
LNA (fRFin = 1575.42 MHz, ZL = ZS = 50 Ω) ZLNAin RF Input Impedance of LNA Ω 28 - j38 ZLNAop RF Out.