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INTEGRATED CIRCUITS
DATA SHEET
UJA1061 Low speed CAN/LIN system basis chip
Objective specificatio...
www.DataSheet4U.com
INTEGRATED CIRCUITS
DATA SHEET
UJA1061 Low speed CAN/LIN system basis chip
Objective specification
2004 Mar 22
Philips Semiconductors
Low speed CAN/LIN system basis chip
Objective specification
UJA1061
CONTENTS
1
1.1 1.2 1.3 1.4 1.5
2
3
4
5
6
6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.7 6.7.1 6.7.2 6.7.3 6.8 6.8.1 6.8.2
FEATURES
General System features Fail-safe features CAN physical layer LIN physical layer
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Introduction Fail-safe system controller Fail-safe mode Start-up mode Restart mode Normal mode Standby mode Sleep mode Flash mode On-chip oscillator Watchdog Watchdog start-up behaviour Watchdog window behaviour Watchdog time-out behaviour Watchdog OFF behaviour System reset System reset pin RSTN Enable output pin EN Power supplies Supported battery systems Static and dynamic battery monitoring
Voltage regulators V1 and V2 Switched battery output (V3) CAN transceiver Mode control Termination control Bus, RXD and TXD failure detection LIN transceiver Mode control Bus and TXDL failure detection
6.9 6.10 6.11 6.12 6.13 6.14 6.14.1 6.14.2 6.14.3 6.14.4 6.14.5 6.14.6 6.14.7 6.14.8 6.14.9 6.14.10 6.14.11 6.14.12 6.14.13 6.14.14 6.15 6.16 6.16.1 6.16.2
7
8
9
10
11
11.1
11.2 11.3 11.4 11.5
12
13
14
Inhibit output (pin INH) Wake-up input (pin WAKE) Interrupt output Temperature protec...