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U5199NL Datasheet

Part Number U5199NL
Manufacturers Vishay Intertechnology
Logo Vishay Intertechnology
Description (U5196NL - U5199NL) Monolithic N-channel JFET Duals
Datasheet U5199NL DatasheetU5199NL Datasheet (PDF)

SST/U5196NL Series New Product Vishay Siliconix Monolithic N-Channel JFET Duals SST5198NL SST5199NL PRODUCT SUMMARY Part Number U5196NL U5197NL U5196NL U5197NL U5198NL U5199NL VGS(off) (V) -0.7 to -4 -0.7 to -4 -0.7 to -4 -0.7 to -4 V(BR)GSS Min (V) -50 -50 -50 -50 gfs Min (mS) 1 1 1 1 IG Max (pA) -15 -15 -15 -15 jVGS1 - VGS2j Max (mV) 5 5 10 15 www.DataSheet4U.com SST/U5198NL SST/U5199NL FEATURES D D D D D D D Anti Latchup Capability Monolithic Design High Slew Rate Low Offset/Drift.

  U5199NL   U5199NL






(U5196NL - U5199NL) Monolithic N-channel JFET Duals

SST/U5196NL Series New Product Vishay Siliconix Monolithic N-Channel JFET Duals SST5198NL SST5199NL PRODUCT SUMMARY Part Number U5196NL U5197NL U5196NL U5197NL U5198NL U5199NL VGS(off) (V) -0.7 to -4 -0.7 to -4 -0.7 to -4 -0.7 to -4 V(BR)GSS Min (V) -50 -50 -50 -50 gfs Min (mS) 1 1 1 1 IG Max (pA) -15 -15 -15 -15 jVGS1 - VGS2j Max (mV) 5 5 10 15 www.DataSheet4U.com SST/U5198NL SST/U5199NL FEATURES D D D D D D D Anti Latchup Capability Monolithic Design High Slew Rate Low Offset/Drift Voltage Low Gate Leakage: 5 pA Low Noise High CMRR: 100 dB BENEFITS D D D D D D D External Substrate Bias—Avoids Latchup Tight Differential Match vs. Current Improved Op Amp Speed, Settling Time Accuracy Minimum Input Error/Trimming Requirement Insignificant Signal Loss/Error Voltage High System Sensitivity Minimum Error with Large Input Signal APPLICATIONS D Wideband Differential Amps D High-Speed, Temp-Compensated, Single-Ended Input Amps D High Speed Comparators D Impedance Converters DESCRIPTION The SST/U5196NL series of JFET duals are designed for high-performance differential amplification for a wide range of precision test instrumentation applications. This series features tightly matched specs, low gate leakage for accuracy, and wide dynamic range with IG guaranteed at VDG = 20 V. Pins 4 and 8 of the SST series and pin 4 on the U series part numbers enable the substrate to be connected to a positive, external bias (VDD) to avoid latchup. Narrow Body SOIC S1 D1 G1 SUBSTRATE .


2008-04-25 : D1761    GM7620    D27512    27512    PL603-27    PL610-01    PL611-01    PL611-05    PL611-07    PL611-20   


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