TP5322

TP5322 TP5322 www.DataSheet4U.com Initial Release P-Channel Enhancement-Mode Vertical DMOS FET General Description These low threshold enhancement-mode (normally-off) transistors utilize an advanced vertical DMOS structure and Supertex's well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. Supertex's vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Features ! ! ! ! ! ! ! ! Low threshold, -2.4V max. High input impedance Low input capacitance, 110pFmax. Fast switching speeds Low on resistance Free from secondary breakdown Low input and output leakage Complementary N- and P-channel devices Application ! ! ! ! ! ! Logic level interfaces-ideal for TTL and CMOS Battery operated systems Photo voltaic devices Analog switches General purpose line drivers Telecom switches Package Options D D Absolute Maximum Ratings Drain-to-Source Voltage Drain-to-Gate Voltage Gate-to-Source Voltage Operating and Storage Temperature Soldering Temperature**** ****Distance of 1.6mm from case for 10 seconds. ...