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TL071B Datasheet

Part Number TL071B
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description Low noise JFET single operational amplifier
Datasheet TL071B DatasheetTL071B Datasheet (PDF)

TL071 Low noise JFET single operational amplifier Features ■ Wide common-mode (up to VCC+) and differential voltage range ■ Low input bias and offset currenT ■ Low noise en = 15 nV/ √Hz (typ) ■ Output short-circuit protection ■ High input impedance JFET input stage ■ Low harmonic distortion: 0.01 % (typ) ■ Internal frequency compensation ■ Latch-up free operation ■ High slew rate: 16 V /µs (typ) Description The TL071 is a high-speed JFET input single operational amplifier. This JFET input opera.

  TL071B   TL071B






Part Number TL071B
Manufacturers Texas Instruments
Logo Texas Instruments
Description Low-Noise JFET-Input Operational Amplifiers
Datasheet TL071B DatasheetTL071B Datasheet (PDF)

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M SLOS080V – SEPTEMBER 1978 – REVISED APRIL 2023 TL07xx Low-Noise FET-Input Operational Amplifiers 1 Features • High slew rate: 20 V/μs (TL07xH, typ) • Low offset voltage: 1 mV (TL07xH, typ) • Low offset voltage drift: 2 μV/°C • Low power consumption: 940 μA/ch (TL07xH, typ) • Wide common-mode and differential voltage ranges – Common-mode input voltage range includes VCC+ • Low input bias and.

  TL071B   TL071B







Low noise JFET single operational amplifier

TL071 Low noise JFET single operational amplifier Features ■ Wide common-mode (up to VCC+) and differential voltage range ■ Low input bias and offset currenT ■ Low noise en = 15 nV/ √Hz (typ) ■ Output short-circuit protection ■ High input impedance JFET input stage ■ Low harmonic distortion: 0.01 % (typ) ■ Internal frequency compensation ■ Latch-up free operation ■ High slew rate: 16 V /µs (typ) Description The TL071 is a high-speed JFET input single operational amplifier. This JFET input operational amplifier incorporates well matched, high-voltage JFET and bipolar transistors in a monolithic integrated circuit. The device features high slew rates, low input bias and offset currents, and low offset voltage temperature coefficient. N DIP8 (Plastic package) D SO-8 (Plastic micropackage) Pin connections (Top view) 1 8 2 7 3 6 4 5 1 - Offset null 1 2 - Inverting input 3 - Non-inverting input 4 - VCC5 - Offset null 2 6 - Output 7 - VCC+ 8 - N.C. September 2008 Rev 3 1/15 www.st.com 15 Schematic diagram 1 Schematic diagram Figure 1. Circuit schematics V CC Non-inverting input Inverting input TL071 100 Ω 200 Ω 100 Ω 30k Output 8.2k 1.3k 35k 1.3k 35k 100 Ω V CC Offset Null1 Offset Null2 Figure 2. Input offset voltage null circuit TL071 N1 N2 100k Ω V CC 2/15 TL071 2 Absolute maximum ratings and operating conditions Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings Symbol Parameter Value Unit TL071M, AM.


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