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TC74HC237AF Datasheet

Part Number TC74HC237AF
Manufacturers Toshiba
Logo Toshiba
Description 3-TO-8 LINE DECODER/LATCH
Datasheet TC74HC237AF DatasheetTC74HC237AF Datasheet (PDF)

TC74HC237AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC237AP, TC74HC237AF 3-to-8 Line Decoder/Latch The TC74HC237A is a high speed CMOS 3-to-8 LINE DECODER ADDRESS LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It is composed of a 3-bit input latches with a common GL enable input and 3-to-8 line decoder with enable inputs G1 and G2 . The 3-bit binary .

  TC74HC237AF   TC74HC237AF






Part Number TC74HC237AP
Manufacturers Toshiba
Logo Toshiba
Description 3-TO-8 LINE DECODER/LATCH
Datasheet TC74HC237AF DatasheetTC74HC237AP Datasheet (PDF)

TC74HC237AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC237AP, TC74HC237AF 3-to-8 Line Decoder/Latch The TC74HC237A is a high speed CMOS 3-to-8 LINE DECODER ADDRESS LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It is composed of a 3-bit input latches with a common GL enable input and 3-to-8 line decoder with enable inputs G1 and G2 . The 3-bit binary .

  TC74HC237AF   TC74HC237AF







3-TO-8 LINE DECODER/LATCH

TC74HC237AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC237AP, TC74HC237AF 3-to-8 Line Decoder/Latch The TC74HC237A is a high speed CMOS 3-to-8 LINE DECODER ADDRESS LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It is composed of a 3-bit input latches with a common GL enable input and 3-to-8 line decoder with enable inputs G1 and G2 . The 3-bit binary data is stored into the input latch on the high level of GL . The value of this data determines which one of the outputs will go low. When the enable input G1 is held low or G2 is held high, decoding function is inhibited and all the 8 outputs go high. The two enable inputs are provided to ease cascade connection and permits the application address decoder for memory system. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High s.


2018-04-09 : NL10276AC30-48D    PS219B3-CS    PS219B3-ST    PS219B3-AST    PS219B3-CST    IT8782F    LJ8A3-2-Z-BX    CA18FLF08NA    DSTD102    DSTD101   


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