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SY89873L Datasheet

Part Number SY89873L
Manufacturers Micrel Semiconductor
Logo Micrel Semiconductor
Description IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TERMINATION
Datasheet SY89873L DatasheetSY89873L Datasheet (PDF)

Micrel, Inc. 3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS SY89873L ® Precision Edge PROGRAMMABLE CLOCK DIVIDER SY89873L FANOUT BUFFER W/ INTERNAL TERMINATION Precision Edge® FEATURES ■ Guaranteed AC performance Precision Edge® • > 2.0GHz fMAX output toggle • > 3.0GHz fMAX input DESCRIPTION • < 800ps tPD (matched-delay between banks) • < 15ps within-device skew This 3.3V low-skew, low-jitter, precision LVDS output clock • < 190ps rise/fall time divider accepts any high-speed differential clock input (AC-.

  SY89873L   SY89873L






IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TERMINATION

Micrel, Inc. 3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS SY89873L ® Precision Edge PROGRAMMABLE CLOCK DIVIDER SY89873L FANOUT BUFFER W/ INTERNAL TERMINATION Precision Edge® FEATURES ■ Guaranteed AC performance Precision Edge® • > 2.0GHz fMAX output toggle • > 3.0GHz fMAX input DESCRIPTION • < 800ps tPD (matched-delay between banks) • < 15ps within-device skew This 3.3V low-skew, low-jitter, precision LVDS output clock • < 190ps rise/fall time divider accepts any high-speed differential clock input (AC- or ■ Low jitter design DC-coupled) CML, LVPECL, HSTL or LVDS and divides down • < 1psRMS cycle-to-cycle jitter the frequency using a programmable divider ratio to create a • < 10psPP total jitter frequency-locked, lower speed version of the input clock. The ■ Unique input termination and VT pin for DC-coupled SY89873L includes two output banks. Bank A is an exact and AC-coupled inputs: any differential inputs copy of the input clock (pass through) with matched (LVPECL, LVDS, CML, HSTL) propagation delay to Bank B, the divided output bank. Available ■ Precision differential LVDS outputs divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, ■ Matched delay: all outputs have matched delay, 77MHz or 38MHz auxiliary clock components. independent of divider setting The differential input buffer has a unique internal termination ■ TTL/CMOS inputs for select and reset/disable design that allows access to the termination network .


2007-05-03 : AA4002    AA4040PBC    AA8227    AH211    AH266    AH266    AH276    AH277A    AH278    AM4406   


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