STV2050A

STV2050A AUTOMATIC MULTISCAN DIGITAL CONVERGENCE PROCESSOR s s s s s s s s s s s s s Multiscan 1H, 2H, HDTV and SVGA applications 6 Convergence channels 14-bit embedded DACs 1 Focus channel Second order interpolation in vertical direction Digital filtering in horizontal direction On-chip PLL On-chip video pattern generator Automatic compensation of temperature drift and aging of external components Pattern and synchronisation signals for optional optical sensor support Adjustable horizontal and vertical size Up to 7 different data sets Self-controlled power-on sequence Package: PQFP80 Power Supply: 3.3 V Tape and Reel: STV2050ATR Figure 1. Functional Block Diagram RAM H/V Sync Frame and Line Timebase Security Control Horizontal and Vertical Defection Corrections HR HG HB VR VG VB Focus R G B Focus I²C Control EEPROM Interface Pattern Generator September 2003 1/83 Table of Contents 1 GENERAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 SYSTEM BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 DEVICE BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 APPLICATION CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 PIN DESCRIPTION AND PINOUT DIAGRAM . . . . . . . . . . . . . . . . . . . ...