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SP8691

Plessey

(SP8690 / SP8691) ECL Variable Modulus Divider

www.DataSheet4U.com ADVANCE INFORMATION DS3647-1·2 SP8690 200MHz410/11 SP8691 200MHz48/9 The SP8690 and SP8691 are low...


Plessey

SP8691

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www.DataSheet4U.com ADVANCE INFORMATION DS3647-1·2 SP8690 200MHz410/11 SP8691 200MHz48/9 The SP8690 and SP8691 are low power ECL variable modulus dividers, with both ECL10K and TTL/CMOS compatible outputs. They divide by the lower division ratio when either of the ECL control inputs, PE1 or PE2, is in the high state and by the higher ratio when both are low (or open circuit). CLOCK INPUT 1 2 3 4 5 6 7 8 16 15 14 CLOCK INPUT NC NC NC VEE TTL/CMOS OUTPUT NC ECL OUTPUT FEATURES  PE1 CONTROL INPUTS   PE2 NC VCC NC NC I ECL and TTL/CMOS Compatible Outputs I AC-Coupled Input I Control Inputs ECL Compatible QUICK REFERENCE DATA SP8690 SP8691 13 12 11 10 ECL OUTPUT 9 I Supply Voltage: 25·2V60·25V (ECL), 5V60·25V (TTL) I Power Consumption: 70mW (Typ.) I Temperature Range: 255°C to 1125°C (A Grade) 230°C to 170°C (B Grade) DG16 Fig. 1 Pin connections - top view ABSOLUTE MAXIMUM RATINGS Supply voltage, |VCC2VEE| ECL output current Storage temperature range Max. junction temperature TTL output voltage Input voltage Max. open collector current 8V 10mA 265°C to 1150°C 1175°C 112V 2·5V p-p 15mA ORDERING INFORMATION SP8690 A DG SP8690 B DG SP8691 A DG 5962-87678 (SMD) (SP8690) VCC 5 D1 PE1 PE2 CLOCK INPUT CLOCK INPUT 2 3 Q1 D2 Q2 D3 Q3 D4 Q4 8 ECL OUTPUT Q4 1 16 12 VEE 9 ECL OUTPUT 11 TTL/CMOS OUTPUT Fig. 2 Functional diagram (SP8690) SP8690/SP8691 VCC 5 PE1 PE2 2 3 D1 Q1 D2 Q2 D3 Q3 D4 Q4 8 ECL OUTPUT Q2 CLOCK INPUT CLOCK INPUT 1 16 12 VEE Q4...




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