SN75ALS053

SN75ALS053 QUADRUPLE FUTUREBUS TRANSCEIVER SLLS034B – JANUARY 1988 – REVISED MAY 1995 D High-Speed Quadruple Transceiver D Meets or Exceeds Requirements of IEEE N PACKAGE (TOP VIEW) Std. 896.1 – 1987 D Drives Load Impedances as Low as 10 Ω D High-Speed Advanced Low-Power Schottky VCC D1 R1 1 2 3 20 BG GND 19 BUS GND 18 B1 Circuits D2 4 17 B2 D Low Power Dissipation . . . 81 mW Max per Channel D High-Impedance PNP Inputs D BTL™ Logic Level 1-V Bus Swing Reduces Power Consumption D Low Bus-Port Capacitance R2 LOGIC GND D3 R3 D4 R4 5 6 7 8 9 10 16 BUS GND 15 B3 14 B4 13 BUS GND 12 RE 11 TE D Power-Up/Power-Down Protection (Glitch Free) FN PACKAGE (TOP VIEW) R1 D1 VCC BG GND BUS GND D Open-Collector Driver Outputs Allows Wired-OR Connections D Multiple Bus Channel Ground Returns to Reduce Channel Noise Interference D Designed to be a Faster, Lower Power Functional Equivalent of the National Semiconductor DS3893 D2 R2 LOGIC GND 3 2 1 20 19 4 18 5 17 6 16 B1 B2 BUS GND description The SN75ALS053 is a four-channel, monolithic, D3 7 15 B3 R3 8 14 B4 9 10 11 12 13 D4 R4 TE RE BUS GND high-speed, advanced low-power Schottky de- vice designed for two-way data communication in a densely populated backplane. The SN75ALS053 has independent driver input (Dn) and receiver output (Rn) pins and separate driver and receiver disables. This transceiver is designed for use in high-speed bus systems and is similar to the SN75ALS057 transceiver except that the ...