SN54BCT573

D Operating Voltage Range of 4.5 V to 5.5 V D State-of-the-Art BiCMOS Design Significantly Reduces ICCZ D Full Parallel Access for Loading SN54BCT573 . . . J OR W PACKAGE SN74BCT573 . . . DW, N, OR NS PACKAGE (TOP VIEW) SN54BCT573, SN74BCT573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS071B − AUGUST 1990 − REVISED MARCH 2003 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) SN54BCT573 . . . FK PACKAGE (TOP VIEW) 1Q VCC OE 1D 2D OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE description/ordering information 8D GND LE 3 2 1 20 19 3D 4 18 2Q 4D 5 17 3Q 5D 6 16 4Q 6D 7 15 5Q 7D 8 14 6Q 9 10 11 12 13 8Q 7Q These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ’BCT573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels that were set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In t...