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SM8211M

Nippon Precision Circuits Inc

POCSAG Decoder For Pagers

SM8211M NIPPON PRECISION CIRCUITS INC. POCSAG Decoder For Pagers OVERVIEW The SM8211M is a POCSAG-standard (Post Office...


Nippon Precision Circuits Inc

SM8211M

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SM8211M NIPPON PRECISION CIRCUITS INC. POCSAG Decoder For Pagers OVERVIEW The SM8211M is a POCSAG-standard (Post Office Code Standardization Advisory Group) signal processor LSI, which conforms to CCIR recommendation 584 concerning standard international wireless calling codes. The SM8211M supports call messages in either tone, numerical or character outputs at signal speeds of 512 bps or 1200 bps using a 76.8 kHz system clock, or 2400 bps using a double-speed 153.6 kHz system clock. Note that output timing values for 2400 bps mode operation are not shown in this datasheet, but can be obtained by halving the values for 1200 bps mode operation. CMOS structure and low-voltage operation realize low power dissipation, plus an intermittent-duty receive method (battery-saving function) reduces battery consumption. The SM8211M is available in 20-pin SSOPs. s s s s Built-in input signal filter, with filter ON/OFF and 4 selectable filter characteristics 1.2 to 3.5 V (76.8 kHz system clock) or 2.0 to 3.5 V (153.6 kHz system clock) operating supply voltage Molybdenum-gate CMOS process realizes low power dissipation 20-pin SSOP PINOUT XVDD BS1 BS2 BS3 VDD TEST1 TEST2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 XTN XT SYN-VAL RX-CLK ADD-DET VSS SIG-IN BACKUP RX-DATA RST SM8211M FEATURES s s s s TX-CLK TX-DATA BREAK s s 4 4 0.68 0.12 s s s s s s NIPPON PRECISION CIRCUITS—1 0.15 − 0.10 + 0.05 0.30 0.15 1.80 0.05 0.60 0.15 s Conforms to POCSAG standard for pag...




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