SLGSSTVF16859H

SLGSSTVF16859H/V DDR 13 to 26 Bit Registered Buffer Applications: PC1600/2100/2700/3200 DDR memory modules 1:2 Outputs for stacked DDR DIMMS SSTL_2 compatible data registers Features: Compatible with JEDEC standard SSTV16859 Differential Clock inputs SSTL_2 data input signaling Supports SSTL_2 class I output specifications Output circuitry minimizes effects of SSO and unterminated lines www.DataSheet4U.com LVCMOS input levels on RESET pin 2.3V-2.7V Operation for PC1600/2100/2700 2.5V-2.7V Operation for PC3200 Max Clock frequency > 210MHz Pin Configuration Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ Q5B Q4B Q3B Q2B Q1B Block Diagram CLK 48 CLK 49 RESET 51 D1 35 VREF 45 . . .. R CLK D1 16 . 32 Q1A Q1B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDQ GND D13 D12 VDD VDDQ GND D11 D10 D9 GND D8 D7 RESET GND CLK CLK VDDQ VDD VREF D6 GND D5 D4 D3 GND VDDQ VDD D2 D1 GND VDDQ To 12 other channels 64-Pin TSSOP 6.1mm body, 0.50mm pitch SLGSSTVF16859H Truth Table Inputs RESET L H H H CLK CLK D X, or X, or X, or Floating Floating Floating H L L or H L or H X Q Outputs Q L H L Q0(2) Notes: 1. H = High Signal Level L = Low Signal Level = Transition LOW-to-HIGH = Transition HIGH-to-LOW X = Don’t care 2. Output level prior to indicated stea...