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SCAN92LV090 Datasheet

Part Number SCAN92LV090
Manufacturers National Semiconductor
Logo National Semiconductor
Description 9 Channel Bus LVDS Transceiver with 1149.1 Access
Datasheet SCAN92LV090 DatasheetSCAN92LV090 Datasheet (PDF)

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN February 2005 SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN General Description The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are inte.

  SCAN92LV090   SCAN92LV090






Part Number SCAN92LV090
Manufacturers ETCTI
Logo ETCTI
Description SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN (Rev. I)
Datasheet SCAN92LV090 DatasheetSCAN92LV090 Datasheet (PDF)

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  SCAN92LV090   SCAN92LV090







9 Channel Bus LVDS Transceiver with 1149.1 Access

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN February 2005 SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN General Description The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ± 1V. The receiver threshold is less than ± 100 mV over a ± 1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and the optional Test Reset (TRST). Features IEEE 1149.1 (JTAG) Compliant Bus LVDS Si.


2005-04-08 : LQ2134    MT8870    SMBD2835    SMBD2836    SMBD2837    SMBD2838    SMBD6050    SMBD6100    SMBD7000    SMBD7000   


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