SA-1110 Datasheet
Part Number |
SA-1110 |
Manufacturers |
Intel Corporation |
Logo |
|
Description |
Intel-R StrongARM SA-1110 Microprocessor |
Datasheet |
SA-1110 Datasheet (PDF) |
www.DataSheet4U.com
Intel® StrongARM* SA-1110 Microprocessor
Brief Datasheet
Product Features
The Intel®StrongARM SA-1110 Microprocessor (SA-1110) is a device optimized for meeting portable and embedded application requirements. The SA-1110 incorporates a 32-bit StrongARM RISC processor capable of running at up to 206 MHz. The SA-1110 has a large instruction and data cache, memory-management unit (MMU), and read/write buffers. The SA-1110 memory bus interfaces to many device types including synchronous DRAM (SDRAM), synchronous mask ROM (SMROM), and SRAM-like variable latency I/O devices with a shared data ready signal. In addition, the SA-1110 provides system support logic, multiple serial communication channels, a color/gray scale LCD controller, PCMCIA support for up to two sockets, and general-purpose I/O ports.
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High performance — 150 Dhrystone 2.1 MIPS @ 133 MHz — 235 Dhrystone 2.1 MIPS @ 206 MHz
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Memory bus — Interfaces to ROM, synchronous mask ROM (SMROM), Flash, SRAM, S.
Intel-R StrongARM SA-1110 Microprocessor
www.DataSheet4U.com
Intel® StrongARM* SA-1110 Microprocessor
Brief Datasheet
Product Features
The Intel®StrongARM SA-1110 Microprocessor (SA-1110) is a device optimized for meeting portable and embedded application requirements. The SA-1110 incorporates a 32-bit StrongARM RISC processor capable of running at up to 206 MHz. The SA-1110 has a large instruction and data cache, memory-management unit (MMU), and read/write buffers. The SA-1110 memory bus interfaces to many device types including synchronous DRAM (SDRAM), synchronous mask ROM (SMROM), and SRAM-like variable latency I/O devices with a shared data ready signal. In addition, the SA-1110 provides system support logic, multiple serial communication channels, a color/gray scale LCD controller, PCMCIA support for up to two sockets, and general-purpose I/O ports.
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High performance — 150 Dhrystone 2.1 MIPS @ 133 MHz — 235 Dhrystone 2.1 MIPS @ 206 MHz
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Memory bus — Interfaces to ROM, synchronous mask ROM (SMROM), Flash, SRAM, SRAM-like variable latency I/O, DRAM, and synchronous DRAM (SDRAM) — Supports two PCMCIA sockets
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Low power (normal mode)
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32-way set-associative caches
DataShe
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— <240 mW @1.55 V/133 MHz — 16 Kbyte instruction cache DataSheet4U.com — <400 mW @1.75 V/206 MHz — 8 Kbyte write-back data cache
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Integrated clock generation — Internal phase-locked loop (PLL) — 3.686-MHz oscillator — 32.768-kHz oscillator
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32-entry MMUs — Maps 4 Kbyte, 8 Kbyte, or 1 Mbyte
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Power-management features .
2006-09-24 : MLW-302x MLW-301x MLW3022 C3927 MLW302x MLW301x DV-704A ST7MC1 ST7MC2 MLW-3022