S5933

www.DataSheet4U.com 32-Bit PCI “MatchMaker” February 12, 1997 Revised October 1998 S5933 FEATURES PCI 2.1 Compliant Master/Slave Device Full 132 Mbytes/sec Transfer Rate PCI Bus Operation DC to 33 Mhz 8/16/32 Bit Add-On User Bus Four Definable Pass-Thru Regions Two 32 Byte FIFOs Sync/Async Add-On Bus Operation Mail Box Registers w/Byte Level Status Direct Mail Box Data Strobe/Interrupts Big/Little Endian Conversions Direct PCI & Add-On Interrupt Pins Boot Loading from nvRAM or Byte Wide Optional Expansion BIOS/POST Code 160 Pin PQFP APPLICATIONS High Speed Networking Digital Video Applications I/O Communications Ports High Speed Data Input/Output Multimedia Communications Memory Interfaces High Speed Data Acquisition Data Encryption/Decryption Intel i960 Interface General Purpose PCI Interfacing DESCRIPTION The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing system speed and expansion capabilities. The PCI Local bus moves high speed peripherals from the I/O bus and places them closer to the system’s processor bus, providing faster data transfer between the processor and peripherals. The PCI Local bus also addresses the industry’s need for a standard that is not directly dependent on the speed, size and type of processor bus. It represents the first microprocessor independent bus offering performance more than adequate for the most demanding applications, such ...