5$6- ® +LJK 6SHHG /RZ3RZHU 6LQJOH 3RUW
$0,+* PLFURQ &026 *DWH $UUD\ 0HPRULHV
Features
Self-timed design allows flexibility in clock duty cycle while maintaining fast cycle time
256 x 8 instantiation block Always active outputs Low standby power when the clock is stopped Separate input and output ports with full parallel access Altera F...