32 MHz 32-bit RX MCUs
Datasheet
RX111 Group
Renesas MCUs
R01DS0190EJ0100 Rev.1.00 Jun 19, 2013
32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kby...
Description
Datasheet
RX111 Group
Renesas MCUs
R01DS0190EJ0100 Rev.1.00 Jun 19, 2013
32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory, USB 2.0 full-speed host/function/OTG, up to 6 comms channels, 12-bit A/D, 8-bit D/A, RTC
Features
■ 32-bit RX CPU core 32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle) Fast interrupt CISC Harvard architecture with five-stage pipeline Variable-length instruction format, ultra-compact code On-chip debugging circuit ■ Low power consumption functions Operation from a single 1.8 to 3.6 V supply Three low power consumption modes ■ On-chip flash memory for code, no wait states Operation at 32 MHz, read cycle of 31.25 ns No wait states for reading at full CPU speed 16 to 128 Kbyte capacities Programmable at 1.8 V For instructions and operands ■ On-chip data flash memory 8 Kbytes 1,000,000 Erase/Write cycles (typ.) BGO (Background Operation) ■ On-chip SRAM, no wait states 8 to 16 Kbyte capacities ■ Data transfer controller (DTC) Four transfer modes Transfer can be set for each interrupt source. ■ Event link controller (ELC) Module operation can be initiated by event signals without going through interrupts. Link operation between modules is possible while the C...
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