QL2007

www.DataSheet4U.com 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. E pASIC 2 HIGHLIGHTS ® QL2007 Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance -Design tools produce fast, efficient Verilog/VHDL synthesis Speed, Density, Low Cost and Flexibility in One Device … 7,000 usable ASICgates, 174 I/O pins -16-bit counter speeds exceeding 200 MHz -7,000 usable ASIC gates, 11,000 usable PLD gates, 174 I/Os -3-layer metal ViaLink® process for small die sizes -100% routable and pin-out maintainable 3 pASIC 2 Advanced Logic Cell and I/O Capabilities -Complex functions (up to 16 inputs) in a single logic cell -High synthesis gate utilization from logic cell fragments -Full IEEE Standard JTAG boundary scan capability -Individually-controlled input/feedback registers and OEs on all I/O pins Other Important Family Features -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2007 Block Diagram 480 Logic Cells 3-25 DataSheet 4 U .com www.DataSheet4U.com QL2007 PRODUCT SUMMARY The QL2007 is a 7,000 usable ASIC gate, 11,000 usable PLD gate member of the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination of architecture, technology, and software to...