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PSD854F2 Datasheet

Part Number PSD854F2
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description Flash in-system programmable (ISP) peripherals for 8-bit MCUs
Datasheet PSD854F2 DatasheetPSD854F2 Datasheet (PDF)

PSD8XXFX Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V Features ■ Flash in-system programmable (ISP) peripheral for 8-bit MCUs ■ Dual bank Flash memories )– Up to 2 Mbit of primary Flash memory (8 t(suniform sectors, 32K x8) c– Up to 256 Kbit secondary Flash memory (4 uuniform sectors) rod– Concurrent operation: read from one memory while erasing and writing the other P■ Up to 256 Kbit SRAM te■ 27 reconfigurable I/Oports ole■ Enhanced JTAG serial port s■ PLD with macrocel.

  PSD854F2   PSD854F2






Part Number PSD854F2
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description Flash In-System Programmable ISP Peripherals For 8-bit MCUs
Datasheet PSD854F2 DatasheetPSD854F2 Datasheet (PDF)

PSD8XXFX Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V Features ■ Flash in-system programmable (ISP) peripheral for 8-bit MCUs ■ Dual bank Flash memories )– Up to 2 Mbit of primary Flash memory (8 t(suniform sectors, 32K x8) c– Up to 256 Kbit secondary Flash memory (4 uuniform sectors) rod– Concurrent operation: read from one memory while erasing and writing the other P■ Up to 256 Kbit SRAM te■ 27 reconfigurable I/Oports ole■ Enhanced JTAG serial port s■ PLD with macrocel.

  PSD854F2   PSD854F2







Flash in-system programmable (ISP) peripherals for 8-bit MCUs

PSD8XXFX Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V Features ■ Flash in-system programmable (ISP) peripheral for 8-bit MCUs ■ Dual bank Flash memories )– Up to 2 Mbit of primary Flash memory (8 t(suniform sectors, 32K x8) c– Up to 256 Kbit secondary Flash memory (4 uuniform sectors) rod– Concurrent operation: read from one memory while erasing and writing the other P■ Up to 256 Kbit SRAM te■ 27 reconfigurable I/Oports ole■ Enhanced JTAG serial port s■ PLD with macrocells Ob– Over 3000 gates of PLD: CPLD and DPLD -– CPLD with 16 output macrocells (OMCs) )and 24 input macrocells (IMCs) t(s– DPLD - user defined internal chip select cdecoding du■ 27 individually configurable I/O port pins roThey can be used for the following functions: – MCU I/Os P– PLD I/Os te– Latched MCU address output le– Special function I/Os. so– 16 of the I/O ports may be configured as Ob open-drain outputs. PQFP52 (M) PLCC52 (J) TQFP64 (U) ■ Progr.


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